Code placement techniques for cache miss rate reduction

Hiroyuki Tomiyama, Hiroto Yasuura

研究成果: ジャーナルへの寄稿記事

36 引用 (Scopus)

抄録

In the design of embedded systems with cache memories, it is important to minimize the cache miss rates to reduce power consumption of the systems as well as improve the performance. In this article, we propose two code placement methods (a simplified method and a refined one) to reduce miss rates of instruction caches. We first define a simplified code placement problem without an attempt to minimize the code size. The problem is formulated as an integer linear programming (ILP) problem, by which an optimal placement can be found. Experimental results show that the simplified method reduces cache misses by an average of 30% (max. 77%). However, the code size obtained by the simplified method tends to be large, which inevitably leads to a larger memory size. In order to overcome this limitation, we further propose a refined code placement method in which the code size provided by the system designers must be satisfied. The effectiveness of the refined method is also demonstrated.

元の言語英語
ページ(範囲)410-429
ページ数20
ジャーナルACM Transactions on Design Automation of Electronic Systems
2
発行部数4
DOI
出版物ステータス出版済み - 1 1 1997

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Cache memory
Embedded systems
Linear programming
Electric power utilization
Data storage equipment

All Science Journal Classification (ASJC) codes

  • Computer Science Applications
  • Computer Graphics and Computer-Aided Design
  • Electrical and Electronic Engineering

これを引用

Code placement techniques for cache miss rate reduction. / Tomiyama, Hiroyuki; Yasuura, Hiroto.

:: ACM Transactions on Design Automation of Electronic Systems, 巻 2, 番号 4, 01.01.1997, p. 410-429.

研究成果: ジャーナルへの寄稿記事

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