抄録
We intend to obtain a fast and high-density logic circuit combining neuron MOS transistors (neuMOS), that was developed in Tohoku university, into a binary logic circuit. In this paper, we focus on basic arithmetic functional circuits, a full-adder and a multiplier, and make a comparison of the area and delay of the neuMOS circuits with conventional CMOS logic circuits. The results of physical design and SPICE simulation show that the area of a neuMOS multiplier with full-adders decreases to about 65% of the area of CMOS, and the delay of a neuMOS multiplier with (7,3) parallel counters decreases to about 70% of the delay of CMOS.
| 本文言語 | 英語 |
|---|---|
| ホスト出版物のタイトル | IEEE Asia-Pacific Conference on Circuits and Systems - Proceedings |
| 出版社 | IEEE |
| ページ | 488-491 |
| ページ数 | 4 |
| 出版ステータス | 出版済み - 1996 |
| イベント | Proceedings of the 1996 IEEE Asia Pacific Conference on Circuits and Systems - Seoul, South Korea 継続期間: 11月 18 1996 → 11月 21 1996 |
その他
| その他 | Proceedings of the 1996 IEEE Asia Pacific Conference on Circuits and Systems |
|---|---|
| City | Seoul, South Korea |
| Period | 11/18/96 → 11/21/96 |
!!!All Science Journal Classification (ASJC) codes
- 電子工学および電気工学