Comparison of parallel multipliers with neuron MOS and CMOS technologies

Kei Hirose, Hiroto Yasuura

研究成果: Chapter in Book/Report/Conference proceedingConference contribution

11 被引用数 (Scopus)

抄録

We intend to obtain a fast and high-density logic circuit combining neuron MOS transistors (neuMOS), that was developed in Tohoku university, into a binary logic circuit. In this paper, we focus on basic arithmetic functional circuits, a full-adder and a multiplier, and make a comparison of the area and delay of the neuMOS circuits with conventional CMOS logic circuits. The results of physical design and SPICE simulation show that the area of a neuMOS multiplier with full-adders decreases to about 65% of the area of CMOS, and the delay of a neuMOS multiplier with (7,3) parallel counters decreases to about 70% of the delay of CMOS.

本文言語英語
ホスト出版物のタイトルIEEE Asia-Pacific Conference on Circuits and Systems - Proceedings
出版社IEEE
ページ488-491
ページ数4
出版ステータス出版済み - 1996
イベントProceedings of the 1996 IEEE Asia Pacific Conference on Circuits and Systems - Seoul, South Korea
継続期間: 11 18 199611 21 1996

その他

その他Proceedings of the 1996 IEEE Asia Pacific Conference on Circuits and Systems
CitySeoul, South Korea
Period11/18/9611/21/96

All Science Journal Classification (ASJC) codes

  • 電子工学および電気工学

フィンガープリント

「Comparison of parallel multipliers with neuron MOS and CMOS technologies」の研究トピックを掘り下げます。これらがまとまってユニークなフィンガープリントを構成します。

引用スタイル