Complementary exposure of 70 nm SoC devices in electron projection lithography

Hiroshi Yamashita, Isao Amemiya, Kunio Takeuchi, Hideki Masaoka, Kimitoshi Takahashi, Akihiro Ikeda, Yukinori Kuroki, Masaki Yamabe

研究成果: ジャーナルへの寄稿記事

6 引用 (Scopus)

抜粋

The effectiveness of hierarchical data processing capabilities using Anaheim, a 70 nm system-on-a-chip (SoC) devices in electron projection lithography (EPL) was analyzed. Selete's 10 PC-clustered hierarchical data processing system was used to reduce the data processing time and output data volume of a complementary split by M-Split from 57 to 7.7 min and from 12.4 to 1.7 Gb. The complementary exposure of the Anaheim using Nikon's electron beam (EB) stepper, NSR-EB1A and a high-performance Si stencil mask fabricated by HOYA was performed. The results show that the complementary exposure technique, including a complementary mask pattern split and stencil mask fabrication, is no longer a critical issue for EPL.

元の言語英語
ページ(範囲)2645-2649
ページ数5
ジャーナルJournal of Vacuum Science and Technology B: Microelectronics and Nanometer Structures
21
発行部数6
出版物ステータス出版済み - 11 1 2003

    フィンガープリント

All Science Journal Classification (ASJC) codes

  • Condensed Matter Physics
  • Electrical and Electronic Engineering

これを引用

Yamashita, H., Amemiya, I., Takeuchi, K., Masaoka, H., Takahashi, K., Ikeda, A., ... Yamabe, M. (2003). Complementary exposure of 70 nm SoC devices in electron projection lithography. Journal of Vacuum Science and Technology B: Microelectronics and Nanometer Structures, 21(6), 2645-2649.