CPCI Stack: Metric for Accurate Bottleneck Analysis on OoO Microprocessors

研究成果: Chapter in Book/Report/Conference proceedingConference contribution

1 被引用数 (Scopus)

抄録

Correctly understanding microarchitectural bottlenecks is important to optimize performance and energy of OoO (Out-of-Order) processors. Although CPI (Cycles Per Instruction) stack has been utilized for this purpose, it stacks architectural events heuristically by counting how many times the events occur, and the order of stacking affects the result, which may be misleading. It is because CPI stack does not consider the execution path of dynamic instructions. Critical path analysis (CPA) is a well-known method to identify the critical execution path of dynamic instruction execution on OoO processors. The critical path consists of the sequence of events that determines the execution time of a program on a certain processor. We develop a novel representation of CPCI stack (Cycles Per Critical Instruction stack), which is CPI stack based on CPA. The main challenge in constructing CPCI stack is how to analyze a large number of paths because CPA often results in numerous critical paths. In this paper, we show that there are more than ten to the tenth power critical paths in the execution of only one thousand instructions in 35 benchmarks out of 48 from SPEC CPU2006. Then, we propose a statistical method to analyze all the critical paths and show a case study using the benchmarks.

本文言語英語
ホスト出版物のタイトルProceedings - 2017 5th International Symposium on Computing and Networking, CANDAR 2017
出版社Institute of Electrical and Electronics Engineers Inc.
ページ166-172
ページ数7
ISBN(電子版)9781538620878
DOI
出版ステータス出版済み - 4 23 2018
イベント5th International Symposium on Computing and Networking, CANDAR 2017 - Aomori, 日本
継続期間: 11 19 201711 22 2017

出版物シリーズ

名前Proceedings - 2017 5th International Symposium on Computing and Networking, CANDAR 2017
2018-January

その他

その他5th International Symposium on Computing and Networking, CANDAR 2017
国/地域日本
CityAomori
Period11/19/1711/22/17

All Science Journal Classification (ASJC) codes

  • 人工知能
  • コンピュータ ネットワークおよび通信
  • ハードウェアとアーキテクチャ

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