CPCI Stack: Metric for Accurate Bottleneck Analysis on OoO Microprocessors

研究成果: 著書/レポートタイプへの貢献会議での発言

抄録

Correctly understanding microarchitectural bottlenecks is important to optimize performance and energy of OoO (Out-of-Order) processors. Although CPI (Cycles Per Instruction) stack has been utilized for this purpose, it stacks architectural events heuristically by counting how many times the events occur, and the order of stacking affects the result, which may be misleading. It is because CPI stack does not consider the execution path of dynamic instructions. Critical path analysis (CPA) is a well-known method to identify the critical execution path of dynamic instruction execution on OoO processors. The critical path consists of the sequence of events that determines the execution time of a program on a certain processor. We develop a novel representation of CPCI stack (Cycles Per Critical Instruction stack), which is CPI stack based on CPA. The main challenge in constructing CPCI stack is how to analyze a large number of paths because CPA often results in numerous critical paths. In this paper, we show that there are more than ten to the tenth power critical paths in the execution of only one thousand instructions in 35 benchmarks out of 48 from SPEC CPU2006. Then, we propose a statistical method to analyze all the critical paths and show a case study using the benchmarks.

元の言語英語
ホスト出版物のタイトルProceedings - 2017 5th International Symposium on Computing and Networking, CANDAR 2017
出版者Institute of Electrical and Electronics Engineers Inc.
ページ166-172
ページ数7
2018-January
ISBN(電子版)9781538620878
DOI
出版物ステータス出版済み - 4 23 2018
イベント5th International Symposium on Computing and Networking, CANDAR 2017 - Aomori, 日本
継続期間: 11 19 201711 22 2017

その他

その他5th International Symposium on Computing and Networking, CANDAR 2017
日本
Aomori
期間11/19/1711/22/17

Fingerprint

Critical path analysis
Microprocessor chips
Statistical methods

All Science Journal Classification (ASJC) codes

  • Artificial Intelligence
  • Computer Networks and Communications
  • Hardware and Architecture

これを引用

Tanimoto, T., Ono, T., & Koji, I. (2018). CPCI Stack: Metric for Accurate Bottleneck Analysis on OoO Microprocessors. : Proceedings - 2017 5th International Symposium on Computing and Networking, CANDAR 2017 (巻 2018-January, pp. 166-172). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/CANDAR.2017.60

CPCI Stack : Metric for Accurate Bottleneck Analysis on OoO Microprocessors. / Tanimoto, Teruo; Ono, Takatsugu; Koji, Inoue.

Proceedings - 2017 5th International Symposium on Computing and Networking, CANDAR 2017. 巻 2018-January Institute of Electrical and Electronics Engineers Inc., 2018. p. 166-172.

研究成果: 著書/レポートタイプへの貢献会議での発言

Tanimoto, T, Ono, T & Koji, I 2018, CPCI Stack: Metric for Accurate Bottleneck Analysis on OoO Microprocessors. : Proceedings - 2017 5th International Symposium on Computing and Networking, CANDAR 2017. 巻. 2018-January, Institute of Electrical and Electronics Engineers Inc., pp. 166-172, 5th International Symposium on Computing and Networking, CANDAR 2017, Aomori, 日本, 11/19/17. https://doi.org/10.1109/CANDAR.2017.60
Tanimoto T, Ono T, Koji I. CPCI Stack: Metric for Accurate Bottleneck Analysis on OoO Microprocessors. : Proceedings - 2017 5th International Symposium on Computing and Networking, CANDAR 2017. 巻 2018-January. Institute of Electrical and Electronics Engineers Inc. 2018. p. 166-172 https://doi.org/10.1109/CANDAR.2017.60
Tanimoto, Teruo ; Ono, Takatsugu ; Koji, Inoue. / CPCI Stack : Metric for Accurate Bottleneck Analysis on OoO Microprocessors. Proceedings - 2017 5th International Symposium on Computing and Networking, CANDAR 2017. 巻 2018-January Institute of Electrical and Electronics Engineers Inc., 2018. pp. 166-172
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