TY - GEN
T1 - Datarol-II
T2 - 6th International Conference on Parallel Architectures and Languages Europe, PARLE 1994
AU - Kawano, Tetsuo
AU - Kusakabe, Shigeru
AU - Taniguchi, Rin Ichiro
AU - Amamiya, Makoto
N1 - Publisher Copyright:
© Springer-Verlag Berlin Heidelberg 1994.
PY - 1994
Y1 - 1994
N2 - In this paper, we introduce the Datarol-II processor, that can efficiently execute a fine-grain multi-thread program, called Datarol. In order to achieve the efficient multi-thread execution by reducing context switching overhead, we introduce an implicit register load/store mechanism in the execution pipeline. A two-level hierarchical memory system is also introduced in order to reduce memory access latency. The simulation results show that the Datarol-II processor can tolerate remote memory access latencies and execute a fine-grain multi-thread program efficiently.
AB - In this paper, we introduce the Datarol-II processor, that can efficiently execute a fine-grain multi-thread program, called Datarol. In order to achieve the efficient multi-thread execution by reducing context switching overhead, we introduce an implicit register load/store mechanism in the execution pipeline. A two-level hierarchical memory system is also introduced in order to reduce memory access latency. The simulation results show that the Datarol-II processor can tolerate remote memory access latencies and execute a fine-grain multi-thread program efficiently.
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U2 - 10.1007/3-540-58184-7_156
DO - 10.1007/3-540-58184-7_156
M3 - Conference contribution
AN - SCOPUS:84958763462
SN - 9783540581840
T3 - Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)
SP - 781
EP - 784
BT - PARLE 1994 – Parallel Architectures and Languages Europe - 6th International PARLE Conference, Proceedings
A2 - Halatsis, Costas
A2 - Philokyprou, George
A2 - Maritsas, Dimitrios
A2 - Theodoridis, Sergios
PB - Springer Verlag
Y2 - 4 July 1994 through 8 July 1994
ER -