Design and implementation of low power digital phase-locked loop

M. Saber, Yutaka Jitsumatsu, M. T.A. Khan

研究成果: Chapter in Book/Report/Conference proceedingConference contribution

2 被引用数 (Scopus)

抄録

This paper proposes a low power architecture for second order digital phase-locked loop (DPLL). High power consumption of DPLL results from using a look-up table (LUT) in implementing the numerically controlled oscillator (NCO). A new design for NCO is presented in which no LUT is used. Proposed architecture implemented using field programmable gate array (FPGA) consumed 15.44 mw at 100 MHz clock frequency which means a more than 25% saving in power consumption compared to traditional NCO. Furthermore, proposed method also saves FPGA resources and works at faster clock frequency.

本文言語英語
ホスト出版物のタイトルISITA/ISSSTA 2010 - 2010 International Symposium on Information Theory and Its Applications
ページ928-933
ページ数6
DOI
出版ステータス出版済み - 12 1 2010
イベント2010 20th International Symposium on Information Theory and Its Applications, ISITA 2010 and the 2010 20th International Symposium on Spread Spectrum Techniques and Applications, ISSSTA 2010 - Taichung, 台湾省、中華民国
継続期間: 10 17 201010 20 2010

出版物シリーズ

名前ISITA/ISSSTA 2010 - 2010 International Symposium on Information Theory and Its Applications

その他

その他2010 20th International Symposium on Information Theory and Its Applications, ISITA 2010 and the 2010 20th International Symposium on Spread Spectrum Techniques and Applications, ISSSTA 2010
国/地域台湾省、中華民国
CityTaichung
Period10/17/1010/20/10

All Science Journal Classification (ASJC) codes

  • 計算理論と計算数学
  • 情報システム

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