Design concept of n-buffer layer (n-Bottom Assist Layer) for 600V-class semi-super junction MOSFET

Syotaro Ono, Wataru Saito, Masakatsu Takashita, Shoichiro Kurushima, Ken'ichi Tokano, Masakazu Yamaguchi

研究成果: 書籍/レポート タイプへの寄稿会議への寄与

17 被引用数 (Scopus)

抄録

We report the experimental results detailed about the n-buffer layer (n-BAL: n-Bottom Assist Layer) of 600V-class Semi-SJ MOSFET, and discuss about the design optimization by comparing the trade-off characteristics between the specific on-resistance (RonA) and the breakdown voltage (V B), the avalanche capability and the body diode characteristic for the first time. As design parameters, the thickness ratio TBAL-ratio and the doping concentration NBAL were varied in this work. As a result, the VB=750V, the RonA=24.6mΩcm2, the maximum avalanche current density JAP=292A/cm2 (I AP=7.6A, EAS=1.25J/cm2), and softness factor=0.277 were obtained with the structure of TBAL-ratio=27% and NBAL=1.0×1015 cm-3. The demonstration results showed that NPT (Non Punch Through)-type design (with high T BAL-ratio and high NBAL) realized the larger avalanche capability and the softer reverse recovery characteristic compared with PT (Punch Through)-type design.

本文言語英語
ホスト出版物のタイトルProceedings of 19th International Symposium on Power Semiconductor Devices and ICs, ISPSD'07
ページ25-28
ページ数4
DOI
出版ステータス出版済み - 12月 1 2007
外部発表はい
イベント19th International Symposium on Power Semiconductor Devices and ICs, ISPSD'07 - Jeju Island, 韓国
継続期間: 5月 27 20075月 31 2007

出版物シリーズ

名前Proceedings of the International Symposium on Power Semiconductor Devices and ICs
ISSN(印刷版)1063-6854

その他

その他19th International Symposium on Power Semiconductor Devices and ICs, ISPSD'07
国/地域韓国
CityJeju Island
Period5/27/075/31/07

!!!All Science Journal Classification (ASJC) codes

  • 工学(全般)

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