TY - GEN
T1 - Development of highly efficient push-pull power amplifier with center tapped transformer for 5GHz application
AU - Sadakiyo, Tomoki
AU - Kanaya, Haruichi
N1 - Funding Information:
This work was partly supported by VLSI Design and Education Center (VDEC), the University of Tokyo in collaboration with CADENCE Corporation and Keysight Technologies. This work was also supported in part by a Grant-in-Aid for KAKENHI and CREST.
Publisher Copyright:
© 2017 IEEE.
PY - 2018/1/31
Y1 - 2018/1/31
N2 - This paper presents the design of a highly efficient push-pull power amplifier (PA) for 5.2 GHz band in a 0.18-μm CMOS technology. This PA assumes 802.11ac, which requires linearity, and enables high-speed communication. In this PA, center tapped transformer designed using a 0.18-μm CMOS technology is used. PA had been simulated and measured. The proposed PA has a simulated power-added efficiency (PAE) in the linear operation of 15.7 %, maximum PAE of 30.9 % at 5.2 GHz.
AB - This paper presents the design of a highly efficient push-pull power amplifier (PA) for 5.2 GHz band in a 0.18-μm CMOS technology. This PA assumes 802.11ac, which requires linearity, and enables high-speed communication. In this PA, center tapped transformer designed using a 0.18-μm CMOS technology is used. PA had been simulated and measured. The proposed PA has a simulated power-added efficiency (PAE) in the linear operation of 15.7 %, maximum PAE of 30.9 % at 5.2 GHz.
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U2 - 10.1109/EPTC.2017.8277476
DO - 10.1109/EPTC.2017.8277476
M3 - Conference contribution
AN - SCOPUS:85050631061
T3 - 2017 IEEE 19th Electronics Packaging Technology Conference, EPTC 2017
SP - 1
EP - 4
BT - 2017 IEEE 19th Electronics Packaging Technology Conference, EPTC 2017
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 2017 19th IEEE Electronics Packaging Technology Conference, EPTC 2017
Y2 - 6 December 2017 through 9 December 2017
ER -