Development of low power DAC with pseudo Fibonacci sequence

Ryota Kubokawa, Takashi Ohshima, Abhishek Tomar, Ramesh Pokharel, Haruichi Kanaya, Keiji Yoshida

研究成果: Chapter in Book/Report/Conference proceedingConference contribution

抄録

A 12-bit Digital-analog converter (DAC) with pseudo Fibonacci sequence was fabricated in a 0.18μm CMOS technology. Proposed 12-bit DAC is composed of a 6-bit pseudo Fibonacci sequence and 6bit unary sequence. The power consumption of the proposed DAC is expected lower than that of conventional binary and unary DAC. The simulated power consumption of proposed 12-bit DAC is 40mV at 3.3V supply voltage. Also we fabricated the prototype 6-bit DAC with pseudo Fibonacci sequence and tested. The measured power consumption is very low and almost the same value as a simulated value.

本文言語英語
ホスト出版物のタイトルProceedings of the 2010 Asia Pacific Conference on Circuit and System, APCCAS 2010
ページ370-373
ページ数4
DOI
出版ステータス出版済み - 2010
イベント2010 Asia Pacific Conference on Circuit and System, APCCAS 2010 - Kuala Lumpur, マレーシア
継続期間: 12 6 201012 9 2010

その他

その他2010 Asia Pacific Conference on Circuit and System, APCCAS 2010
国/地域マレーシア
CityKuala Lumpur
Period12/6/1012/9/10

All Science Journal Classification (ASJC) codes

  • 電子工学および電気工学

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