Dynamically variable line-size cache architecture for merged DRAM/Logic LSIs

Koji Inoue, Koji Kai, Kazuaki Murakami

研究成果: ジャーナルへの寄稿学術誌査読

3 被引用数 (Scopus)

抄録

This paper proposes a novel cache architecture suitable for merged DRAM/logic LSIs, which is called dynamically variable line-size cache (D-VLS caché). The D-VLS cache can optimize its line-size according to the characteristic of programs, and attempts to improve the performance by exploiting the high on-chip memory bandwidth on merged DRAM/logic LSIs appropriately. In our evaluation, it is observed that an average memory-access time improvement achieved by a directmapped D-VLS cache is about 20% compared to a conventional direct-mapped cache with fixed 32-byte lines. This performance improvement is better than that of a doubled-size conventional direct-mapped cache*.

本文言語英語
ページ(範囲)1048-1057
ページ数10
ジャーナルIEICE Transactions on Information and Systems
E83-D
5
出版ステータス出版済み - 2000

!!!All Science Journal Classification (ASJC) codes

  • ソフトウェア
  • ハードウェアとアーキテクチャ
  • コンピュータ ビジョンおよびパターン認識
  • 電子工学および電気工学
  • 人工知能

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