Efficient equivalence checker for combinational circuits

研究成果: ジャーナルへの寄稿Conference article

53 引用 (Scopus)

抜粋

This paper describes a novel equivalence checking method for combinational circuits, which utilizes relations among internal signals represented by binary decision diagrams. To verify circuits efficiently, a proper set of internal signals that are independent with each other should be chosen. A heuristic based on analysis of circuit structure is proposed to select such a set of internal signals. The proposed verifier requires only a minute for equivalence checking of all the ISCAS'85 benchmarks on SUN-4/10.

元の言語英語
ページ(範囲)629-634
ページ数6
ジャーナルProceedings - Design Automation Conference
出版物ステータス出版済み - 1 1 1996
外部発表Yes
イベントProceedings of the 1996 33rd Annual Design Automation Conference - Las Vegas, NV, USA
継続期間: 6 3 19966 7 1996

    フィンガープリント

All Science Journal Classification (ASJC) codes

  • Hardware and Architecture
  • Control and Systems Engineering

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