This paper describes a novel equivalence checking method for combinational circuits, which utilizes relations among internal signals represented by binary decision diagrams. To verify circuits efficiently, a proper set of internal signals that are independent with each other should be chosen. A heuristic based on analysis of circuit structure is proposed to select such a set of internal signals. The proposed verifier requires only a minute for equivalence checking of all the ISCAS'85 benchmarks on SUN-4/10.
|ジャーナル||Proceedings - Design Automation Conference|
|出版物ステータス||出版済み - 1 1 1996|
|イベント||Proceedings of the 1996 33rd Annual Design Automation Conference - Las Vegas, NV, USA|
継続期間: 6 3 1996 → 6 7 1996
All Science Journal Classification (ASJC) codes
- Hardware and Architecture
- Control and Systems Engineering