Enhanced dependence graph model for critical path analysis on modern out-of-order processors

研究成果: ジャーナルへの寄稿記事

4 引用 (Scopus)

抄録

The dependence graph model of out-of-order (OoO) instruction execution is a powerful representation used for the critical path analysis. However most, if not all, of the previous models are out-of-date and lack enough detail to model modern OoO processors, or are too specific and complicated which limit their generality and applicability. In this paper, we propose an enhanced dependence graph model which remains simple but greatly improves the accuracy over prior models. The evaluation results using the gem5 simulator show that the proposed enhanced model achieves CPI error of 2.1 percent which is a 90.3 percent improvement against the state-of-the-art model.

元の言語英語
記事番号7882625
ページ(範囲)111-114
ページ数4
ジャーナルIEEE Computer Architecture Letters
16
発行部数2
DOI
出版物ステータス出版済み - 7 1 2017

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Critical path analysis
Simulators

All Science Journal Classification (ASJC) codes

  • Hardware and Architecture

これを引用

Enhanced dependence graph model for critical path analysis on modern out-of-order processors. / Tanimoto, Teruo; Ono, Takatsugu; Inoue, Koji; Sasaki, Hiroshi.

:: IEEE Computer Architecture Letters, 巻 16, 番号 2, 7882625, 01.07.2017, p. 111-114.

研究成果: ジャーナルへの寄稿記事

@article{f7679b4b933e4229a324ddb61c2fc830,
title = "Enhanced dependence graph model for critical path analysis on modern out-of-order processors",
abstract = "The dependence graph model of out-of-order (OoO) instruction execution is a powerful representation used for the critical path analysis. However most, if not all, of the previous models are out-of-date and lack enough detail to model modern OoO processors, or are too specific and complicated which limit their generality and applicability. In this paper, we propose an enhanced dependence graph model which remains simple but greatly improves the accuracy over prior models. The evaluation results using the gem5 simulator show that the proposed enhanced model achieves CPI error of 2.1 percent which is a 90.3 percent improvement against the state-of-the-art model.",
author = "Teruo Tanimoto and Takatsugu Ono and Koji Inoue and Hiroshi Sasaki",
year = "2017",
month = "7",
day = "1",
doi = "10.1109/LCA.2017.2684813",
language = "English",
volume = "16",
pages = "111--114",
journal = "IEEE Computer Architecture Letters",
issn = "1556-6056",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
number = "2",

}

TY - JOUR

T1 - Enhanced dependence graph model for critical path analysis on modern out-of-order processors

AU - Tanimoto, Teruo

AU - Ono, Takatsugu

AU - Inoue, Koji

AU - Sasaki, Hiroshi

PY - 2017/7/1

Y1 - 2017/7/1

N2 - The dependence graph model of out-of-order (OoO) instruction execution is a powerful representation used for the critical path analysis. However most, if not all, of the previous models are out-of-date and lack enough detail to model modern OoO processors, or are too specific and complicated which limit their generality and applicability. In this paper, we propose an enhanced dependence graph model which remains simple but greatly improves the accuracy over prior models. The evaluation results using the gem5 simulator show that the proposed enhanced model achieves CPI error of 2.1 percent which is a 90.3 percent improvement against the state-of-the-art model.

AB - The dependence graph model of out-of-order (OoO) instruction execution is a powerful representation used for the critical path analysis. However most, if not all, of the previous models are out-of-date and lack enough detail to model modern OoO processors, or are too specific and complicated which limit their generality and applicability. In this paper, we propose an enhanced dependence graph model which remains simple but greatly improves the accuracy over prior models. The evaluation results using the gem5 simulator show that the proposed enhanced model achieves CPI error of 2.1 percent which is a 90.3 percent improvement against the state-of-the-art model.

UR - http://www.scopus.com/inward/record.url?scp=85040919232&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=85040919232&partnerID=8YFLogxK

U2 - 10.1109/LCA.2017.2684813

DO - 10.1109/LCA.2017.2684813

M3 - Article

AN - SCOPUS:85040919232

VL - 16

SP - 111

EP - 114

JO - IEEE Computer Architecture Letters

JF - IEEE Computer Architecture Letters

SN - 1556-6056

IS - 2

M1 - 7882625

ER -