Enhancements of a circuit-level timing speculation technique and their evaluations using a co-simulation environment

Yuji Kunitake, Kazuhiro Mima, Toshinori Sato, Hiroto Yasuura

研究成果: ジャーナルへの寄稿記事

1 引用 (Scopus)

抄録

A deep submicron semiconductor technology has increased process variations. This fact makes the estimate of the worst-case design margin difficult. In order to realize robust designs, we are investigating such a typical-case design methodology, which we call Constructive Timing Violation (CTV). In the CTV-based design, we can relax timing constraints. However, relaxing timing constraints might cause some timing errors. While we have applied the CTV-based design to a processor, unfortunately, the timing error recovery has serious impact on processor performance. In this paper, we investigate enhancement techniques of the CTV-based design. In addition, in order to accurately evaluate the CTV- based design, we build a co-simulation framework to consider circuit delay at the architectural level. From the co-simulation results, we find the performance penalty is significantly reduced by the enhancement techniques.

元の言語英語
ページ(範囲)483-491
ページ数9
ジャーナルIEICE Transactions on Electronics
E92-C
発行部数4
DOI
出版物ステータス出版済み - 2009

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Networks (circuits)
Delay circuits
Semiconductor materials

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering
  • Electronic, Optical and Magnetic Materials

これを引用

Enhancements of a circuit-level timing speculation technique and their evaluations using a co-simulation environment. / Kunitake, Yuji; Mima, Kazuhiro; Sato, Toshinori; Yasuura, Hiroto.

:: IEICE Transactions on Electronics, 巻 E92-C, 番号 4, 2009, p. 483-491.

研究成果: ジャーナルへの寄稿記事

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