Evaluation of Residual Stress of Embedded Die Substrate with Hollow Structure for Heterogeneous Integration

Masamitsu Matsuura, Tanemasa Asano, Haruichi Kanaya

研究成果: 書籍/レポート タイプへの寄稿会議への寄与

1 被引用数 (Scopus)

抄録

The residual stress in a silicon die of an embedded die substrate having a hollow structure was investigated. A silicon chip in which piezo-resistance gauges were fabricated was embedded in a hollow chamber inside of the substrate by using a newly developed process technology. The chip was mechanically held with dielectric epoxy resin at the periphery of the chip. Two kinds of the resin having a different coefficient of thermal expansion (CTE) were tested. The residual stress was measured at each critical manufacturing step. The stress was reduced after the formation of the hollow structure. The symmetric structure enabled to minimize the process-induced stress. The use of low CTE resin showed low residual stress.

本文言語英語
ホスト出版物のタイトル2020 IEEE 22nd Electronics Packaging Technology Conference, EPTC 2020
出版社Institute of Electrical and Electronics Engineers Inc.
ページ399-402
ページ数4
ISBN(電子版)9781728189116
DOI
出版ステータス出版済み - 12月 2 2020
イベント22nd IEEE Electronics Packaging Technology Conference, EPTC 2020 - Virtual, Singapore, シンガポール
継続期間: 12月 2 202012月 4 2020

出版物シリーズ

名前2020 IEEE 22nd Electronics Packaging Technology Conference, EPTC 2020

会議

会議22nd IEEE Electronics Packaging Technology Conference, EPTC 2020
国/地域シンガポール
CityVirtual, Singapore
Period12/2/2012/4/20

!!!All Science Journal Classification (ASJC) codes

  • 電子工学および電気工学
  • 安全性、リスク、信頼性、品質管理
  • 電子材料、光学材料、および磁性材料

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