FPGA and ASIC implementations of the ηT pairing in characteristic three

Jean Luc Beuchat, Hiroshi Doi, Kaoru Fujita, Atsuo Inomata, Piseth Ith, Akira Kanaoka, Masayoshi Katouno, Masahiro Mambo, Eiji Okamoto, Takeshi Okamoto, Takaaki Shiga, Masaaki Shirase, Ryuji Soga, Tsuyoshi Takagi, Ananda Vithanage, Hiroyasu Yamamoto

研究成果: ジャーナルへの寄稿学術誌査読

12 被引用数 (Scopus)

抄録

Since their introduction in constructive cryptographic applications, pairings over (hyper)elliptic curves are at the heart of an ever increasing number of protocols. As they rely critically on efficient implementations of pairing primitives, the study of hardware accelerators has become an active research area. In this paper, we propose two coprocessors for the reduced ηT pairing introduced by Barreto et al. as an alternative means of computing the Tate pairing on supersingular elliptic curves. We prototyped our architectures on FPGAs. According to our place-and-route results, our coprocessors compare favorably with other solutions described in the open literature. We eventually present the first ASIC implementation of the reduced ηT pairing.

本文言語英語
ページ(範囲)73-87
ページ数15
ジャーナルComputers and Electrical Engineering
36
1
DOI
出版ステータス出版済み - 1月 2010

!!!All Science Journal Classification (ASJC) codes

  • 制御およびシステム工学
  • コンピュータ サイエンス(全般)
  • 電子工学および電気工学

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