TY - JOUR
T1 - Gate Bias Stress Instability and Hysteresis Characteristics of InAs Nanowire Field-Effect Transistors
AU - Lan, Changyong
AU - Yip, Sen Po
AU - Kang, Xiaolin
AU - Meng, You
AU - Bu, Xiuming
AU - Ho, Johnny C.
N1 - Funding Information:
This research was financially supported by the General Research Fund (CityU 11211317) and the Theme-based Research (T42-103/16-N) of the Research Grants Council of Hong Kong SAR, China, the National Natural Science Foundation of China (51672229, 61605024, 61775031, and 62074024), Fundamental Research Funds for the Central Universities (ZYGX2018J056), and UESTC Foundation for the Academic Newcomers Award.
Publisher Copyright:
© 2020 American Chemical Society.
PY - 2020/12/16
Y1 - 2020/12/16
N2 - Because of the excellent electrical properties, III-V semiconductor nanowires are promising building blocks for next-generation electronics; however, their rich surface states inevitably contribute large amounts of charge traps, leading to gate bias stress instability and hysteresis characteristics in nanowire field-effect transistors (FETs). Here, we investigated thoroughly the gate bias stress and hysteresis effects in InAs nanowire FETs. It is observed that the output current decreases together with the threshold voltage shifting to the positive direction when a positive gate bias stress is applied, and vice versa for the negative gate bias stress. For double-sweep transfer characteristics, the significant hysteresis behavior is observed, depending heavily on the sweeping rate and range. On the basis of complementary investigations of these devices, charge traps are confirmed to be the dominant factor for these instability effects. Importantly, the hysteresis can be simulated well by utilizing a combination of the rate equation for electron density and the empirical model for electron mobility. This provides an accurate evaluation of carrier mobility, which is in distinct contrast to the overestimation of mobility when using the transconductance for calculation. All these findings are important for understanding the charge trap dynamics to further enhance the device performance of nanowire FETs.
AB - Because of the excellent electrical properties, III-V semiconductor nanowires are promising building blocks for next-generation electronics; however, their rich surface states inevitably contribute large amounts of charge traps, leading to gate bias stress instability and hysteresis characteristics in nanowire field-effect transistors (FETs). Here, we investigated thoroughly the gate bias stress and hysteresis effects in InAs nanowire FETs. It is observed that the output current decreases together with the threshold voltage shifting to the positive direction when a positive gate bias stress is applied, and vice versa for the negative gate bias stress. For double-sweep transfer characteristics, the significant hysteresis behavior is observed, depending heavily on the sweeping rate and range. On the basis of complementary investigations of these devices, charge traps are confirmed to be the dominant factor for these instability effects. Importantly, the hysteresis can be simulated well by utilizing a combination of the rate equation for electron density and the empirical model for electron mobility. This provides an accurate evaluation of carrier mobility, which is in distinct contrast to the overestimation of mobility when using the transconductance for calculation. All these findings are important for understanding the charge trap dynamics to further enhance the device performance of nanowire FETs.
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U2 - 10.1021/acsami.0c17317
DO - 10.1021/acsami.0c17317
M3 - Article
C2 - 33287538
AN - SCOPUS:85097782055
VL - 12
SP - 56330
EP - 56337
JO - ACS applied materials & interfaces
JF - ACS applied materials & interfaces
SN - 1944-8244
IS - 50
ER -