Gate Bias Stress Instability and Hysteresis Characteristics of InAs Nanowire Field-Effect Transistors

Changyong Lan, Sen Po Yip, Xiaolin Kang, You Meng, Xiuming Bu, Johnny C. Ho

研究成果: Contribution to journalArticle査読

抄録

Because of the excellent electrical properties, III-V semiconductor nanowires are promising building blocks for next-generation electronics; however, their rich surface states inevitably contribute large amounts of charge traps, leading to gate bias stress instability and hysteresis characteristics in nanowire field-effect transistors (FETs). Here, we investigated thoroughly the gate bias stress and hysteresis effects in InAs nanowire FETs. It is observed that the output current decreases together with the threshold voltage shifting to the positive direction when a positive gate bias stress is applied, and vice versa for the negative gate bias stress. For double-sweep transfer characteristics, the significant hysteresis behavior is observed, depending heavily on the sweeping rate and range. On the basis of complementary investigations of these devices, charge traps are confirmed to be the dominant factor for these instability effects. Importantly, the hysteresis can be simulated well by utilizing a combination of the rate equation for electron density and the empirical model for electron mobility. This provides an accurate evaluation of carrier mobility, which is in distinct contrast to the overestimation of mobility when using the transconductance for calculation. All these findings are important for understanding the charge trap dynamics to further enhance the device performance of nanowire FETs.

本文言語英語
ページ(範囲)56330-56337
ページ数8
ジャーナルACS Applied Materials and Interfaces
12
50
DOI
出版ステータス出版済み - 12 16 2020
外部発表はい

All Science Journal Classification (ASJC) codes

  • Materials Science(all)

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