Gate drive circuit for current balancing of parallel-connected SiC-JFETs under avalanche mode

Taro Takamori, Keiji Wada, Wataru Saito, Shin ichi Nishizawa

研究成果: ジャーナルへの寄稿学術誌査読

6 被引用数 (Scopus)

抄録

This paper proposes a gate drive circuit for the current balancing of parallel-connected SiC-JFETs under avalanche mode. For a solid-state DC circuit breaker, the power devices have to be connected in parallel to reduce the ON-resistance and increase the current rating. In addition, it is reported that the SiC-JFET is suitable power devices from the viewpoint of both conduction loss and long-term reliability. This paper presents the behavior of current balancing of SiC-JFETs in parallel, and then proposes a design procedure of gate drive circuits. The gate drive circuits can achieve the current balance equalization of parallel-connected SiC-JFETs under avalanche mode. The validity of the proposed gate drive circuit is verified by the experiment that uses 1.2 kV SiC-JFETs in a 400 V system.

本文言語英語
論文番号113776
ジャーナルMicroelectronics Reliability
114
DOI
出版ステータス出版済み - 11月 2020

!!!All Science Journal Classification (ASJC) codes

  • 電子材料、光学材料、および磁性材料
  • 原子分子物理学および光学
  • 安全性、リスク、信頼性、品質管理
  • 凝縮系物理学
  • 表面、皮膜および薄膜
  • 電子工学および電気工学

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