Generating and executing multi-exit custom instructions for an adaptive extensible processor

Hamid Noon, Farhad Mehdipour, Kazuaki Murakami, Koji Inoue, Maziar Goudarzi

研究成果: Chapter in Book/Report/Conference proceedingConference contribution

3 被引用数 (Scopus)

抄録

To improve the performance of embedded processors, an effective technique is collapsing critical computation subgraphs as application-specific instruction set extensions and executing them on custom functional units. The problems of this approach are immense cost and long time of designing. To address these issues, we propose an adaptive extensible processor in which custom instructions (CIs) are generated and added after chip-fabrication. To support this feature, custom functional units are replaced by a reconfigurable matrix of functional units with the capability of conditional execution. Unlike previous proposed CIs, ours can include multiple exits. Experimental results show that multi-exit CIs enhance the performance by 46% in average compared to CIs limited to one basic block. A maximum speedup of 2.89 compared to a 4-issue in-order RISC processor, and a speedup of 1.66 in average, was achieved on MiBench benchmark suite.

本文言語英語
ホスト出版物のタイトルProceedings - 2007 Design, Automation and Test in Europe Conference and Exhibition, DATE 2007
ページ325-330
ページ数6
DOI
出版ステータス出版済み - 2007
イベント2007 Design, Automation and Test in Europe Conference and Exhibition - Nice Acropolis, フランス
継続期間: 4 16 20074 20 2007

出版物シリーズ

名前Proceedings -Design, Automation and Test in Europe, DATE
ISSN(印刷版)1530-1591

その他

その他2007 Design, Automation and Test in Europe Conference and Exhibition
Countryフランス
CityNice Acropolis
Period4/16/074/20/07

All Science Journal Classification (ASJC) codes

  • Engineering(all)

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