Guidelines for mitigating NBTI degradation in on-chip memories

Yuji Kunitake, Toshinori Sato, Hiroto Yasuura, Takanori Hayashida

研究成果: Chapter in Book/Report/Conference proceedingConference contribution

抄録

Negative Bias Temperature Instability (NBTI) is one of the dominant factors determining a device lifetime. NBTI causes a threshold voltage shift on a PMOS transistor. Modern LSI often has large on-chip SRAMs such as cache memories. NBTI affects the SRAM cell as degradation in Static Noise Margin (SNM), which is a measure of the read stability of the cell. Hence, a special technique for mitigating NBTI on on-chip SRAMs is required. We investigate features of NBTI via detailed simulations and find that a stress probability and a stress-recovery cycle are important parameters for mitigating it. These parameters are dependent upon the values stored in the cell and the value is dependent upon the on-chip memory configurations and applications. This paper presents the relationship among NBTI degradation, memory configurations, and target applications by focusing on the values stored in SRAM cells. Furthermore, these observations lead us to discuss guidelines for mitigating NBTI degradation of on-chip SRAMs.

本文言語英語
ホスト出版物のタイトル2012 International Symposium on Communications and Information Technologies, ISCIT 2012
ページ822-827
ページ数6
DOI
出版ステータス出版済み - 12 1 2012
イベント2012 International Symposium on Communications and Information Technologies, ISCIT 2012 - Gold Coast, QLD, オーストラリア
継続期間: 10 2 201210 5 2012

出版物シリーズ

名前2012 International Symposium on Communications and Information Technologies, ISCIT 2012

その他

その他2012 International Symposium on Communications and Information Technologies, ISCIT 2012
Countryオーストラリア
CityGold Coast, QLD
Period10/2/1210/5/12

All Science Journal Classification (ASJC) codes

  • Computer Networks and Communications
  • Information Systems

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