Guidelines for mitigating NBTI degradation in on-chip memories

Yuji Kunitake, Toshinori Sato, Hiroto Yasuura, Takanori Hayashida

研究成果: 著書/レポートタイプへの貢献会議での発言

抄録

Negative Bias Temperature Instability (NBTI) is one of the dominant factors determining a device lifetime. NBTI causes a threshold voltage shift on a PMOS transistor. Modern LSI often has large on-chip SRAMs such as cache memories. NBTI affects the SRAM cell as degradation in Static Noise Margin (SNM), which is a measure of the read stability of the cell. Hence, a special technique for mitigating NBTI on on-chip SRAMs is required. We investigate features of NBTI via detailed simulations and find that a stress probability and a stress-recovery cycle are important parameters for mitigating it. These parameters are dependent upon the values stored in the cell and the value is dependent upon the on-chip memory configurations and applications. This paper presents the relationship among NBTI degradation, memory configurations, and target applications by focusing on the values stored in SRAM cells. Furthermore, these observations lead us to discuss guidelines for mitigating NBTI degradation of on-chip SRAMs.

元の言語英語
ホスト出版物のタイトル2012 International Symposium on Communications and Information Technologies, ISCIT 2012
ページ822-827
ページ数6
DOI
出版物ステータス出版済み - 2012
イベント2012 International Symposium on Communications and Information Technologies, ISCIT 2012 - Gold Coast, QLD, オーストラリア
継続期間: 10 2 201210 5 2012

その他

その他2012 International Symposium on Communications and Information Technologies, ISCIT 2012
オーストラリア
Gold Coast, QLD
期間10/2/1210/5/12

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Static random access storage
Data storage equipment
Degradation
Cache memory
Negative bias temperature instability
Threshold voltage
Transistors
Recovery

All Science Journal Classification (ASJC) codes

  • Computer Networks and Communications
  • Information Systems

これを引用

Kunitake, Y., Sato, T., Yasuura, H., & Hayashida, T. (2012). Guidelines for mitigating NBTI degradation in on-chip memories. : 2012 International Symposium on Communications and Information Technologies, ISCIT 2012 (pp. 822-827). [6381015] https://doi.org/10.1109/ISCIT.2012.6381015

Guidelines for mitigating NBTI degradation in on-chip memories. / Kunitake, Yuji; Sato, Toshinori; Yasuura, Hiroto; Hayashida, Takanori.

2012 International Symposium on Communications and Information Technologies, ISCIT 2012. 2012. p. 822-827 6381015.

研究成果: 著書/レポートタイプへの貢献会議での発言

Kunitake, Y, Sato, T, Yasuura, H & Hayashida, T 2012, Guidelines for mitigating NBTI degradation in on-chip memories. : 2012 International Symposium on Communications and Information Technologies, ISCIT 2012., 6381015, pp. 822-827, 2012 International Symposium on Communications and Information Technologies, ISCIT 2012, Gold Coast, QLD, オーストラリア, 10/2/12. https://doi.org/10.1109/ISCIT.2012.6381015
Kunitake Y, Sato T, Yasuura H, Hayashida T. Guidelines for mitigating NBTI degradation in on-chip memories. : 2012 International Symposium on Communications and Information Technologies, ISCIT 2012. 2012. p. 822-827. 6381015 https://doi.org/10.1109/ISCIT.2012.6381015
Kunitake, Yuji ; Sato, Toshinori ; Yasuura, Hiroto ; Hayashida, Takanori. / Guidelines for mitigating NBTI degradation in on-chip memories. 2012 International Symposium on Communications and Information Technologies, ISCIT 2012. 2012. pp. 822-827
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