Hardware based scalable path computation engine for multilayer traffic engineering in GMPLS networks

Shimizu Sho, Kihara Taku, Yutaka Arakawa, Yamanaka Naoaki, Shiba Kosuke

研究成果: Contribution to conferencePaper査読

抄録

A parallel data-flow hardware based path computation engine that makes multilayer traffic engineering more scalable is proposed. The engine achieves 100 times faster than conventional path computation scheme.

本文言語英語
DOI
出版ステータス出版済み - 12 1 2008
外部発表はい
イベント2008 34th European Conference on Optical Communication, ECOC 2008 - Brussels, ベルギー
継続期間: 9 21 20089 25 2008

その他

その他2008 34th European Conference on Optical Communication, ECOC 2008
Countryベルギー
CityBrussels
Period9/21/089/25/08

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering
  • Electronic, Optical and Magnetic Materials

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