HARDWARE MAZE ROUTER WITH APPLICATION TO INTERACTIVE RIP-UP AND REROUTE.

Kei Suzuki, Yusuke Matsunaga, Masayoshi Tachibana, Tatsuo Ohtsuki

研究成果: ジャーナルへの寄稿学術誌査読

13 被引用数 (Scopus)

抄録

A parallel-processing architecture for hardware routers based on the Lee algorithm is presented. Unlike the existing machines, which require N**2 processors to implement the Lee algorithm on an N multiplied by N grid plane, the proposed architecture requires only O(N) processors to find a path in O(N) time. A prototype machine with 64 processors has been developed to deal with a 128 multiplied by 128 grid plane. The architecture of the machine is discussed, together with its experimental performance data. The parallel processed Lee algorithm is most useful and powerful when applied to interactive rip-up and reroute.

本文言語英語
ジャーナルIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
CAD-5
4
出版ステータス出版済み - 10月 1 1986
外部発表はい

All Science Journal Classification (ASJC) codes

  • ソフトウェア
  • コンピュータ グラフィックスおよびコンピュータ支援設計
  • 電子工学および電気工学

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