HARDWARE MAZE ROUTER WITH APPLICATION TO INTERACTIVE RIP-UP AND REROUTE.

Kei Suzuki, Yusuke Matsunaga, Masayoshi Tachibana, Tatsuo Ohtsuki

研究成果: ジャーナルへの寄稿記事

13 引用 (Scopus)

抄録

A parallel-processing architecture for hardware routers based on the Lee algorithm is presented. Unlike the existing machines, which require N**2 processors to implement the Lee algorithm on an N multiplied by N grid plane, the proposed architecture requires only O(N) processors to find a path in O(N) time. A prototype machine with 64 processors has been developed to deal with a 128 multiplied by 128 grid plane. The architecture of the machine is discussed, together with its experimental performance data. The parallel processed Lee algorithm is most useful and powerful when applied to interactive rip-up and reroute.

元の言語英語
ジャーナルIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
CAD-5
発行部数4
出版物ステータス出版済み - 10 1 1986
外部発表Yes

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Routers
Hardware
Processing

All Science Journal Classification (ASJC) codes

  • Software
  • Computer Graphics and Computer-Aided Design
  • Electrical and Electronic Engineering

これを引用

HARDWARE MAZE ROUTER WITH APPLICATION TO INTERACTIVE RIP-UP AND REROUTE. / Suzuki, Kei; Matsunaga, Yusuke; Tachibana, Masayoshi; Ohtsuki, Tatsuo.

:: IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 巻 CAD-5, 番号 4, 01.10.1986.

研究成果: ジャーナルへの寄稿記事

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