抄録
A parallel-processing architecture for hardware routers based on the Lee algorithm is presented. Unlike the existing machines, which require N**2 processors to implement the Lee algorithm on an N multiplied by N grid plane, the proposed architecture requires only O(N) processors to find a path in O(N) time. A prototype machine with 64 processors has been developed to deal with a 128 multiplied by 128 grid plane. The architecture of the machine is discussed, together with its experimental performance data. The parallel processed Lee algorithm is most useful and powerful when applied to interactive rip-up and reroute.
| 元の言語 | 英語 |
|---|---|
| ジャーナル | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems |
| 巻 | CAD-5 |
| 発行部数 | 4 |
| 出版物ステータス | 出版済み - 10 1 1986 |
| 外部発表 | Yes |
Fingerprint
All Science Journal Classification (ASJC) codes
- Software
- Computer Graphics and Computer-Aided Design
- Electrical and Electronic Engineering
これを引用
HARDWARE MAZE ROUTER WITH APPLICATION TO INTERACTIVE RIP-UP AND REROUTE. / Suzuki, Kei; Matsunaga, Yusuke; Tachibana, Masayoshi; Ohtsuki, Tatsuo.
：: IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 巻 CAD-5, 番号 4, 01.10.1986.研究成果: ジャーナルへの寄稿 › 記事
}
TY - JOUR
T1 - HARDWARE MAZE ROUTER WITH APPLICATION TO INTERACTIVE RIP-UP AND REROUTE.
AU - Suzuki, Kei
AU - Matsunaga, Yusuke
AU - Tachibana, Masayoshi
AU - Ohtsuki, Tatsuo
PY - 1986/10/1
Y1 - 1986/10/1
N2 - A parallel-processing architecture for hardware routers based on the Lee algorithm is presented. Unlike the existing machines, which require N**2 processors to implement the Lee algorithm on an N multiplied by N grid plane, the proposed architecture requires only O(N) processors to find a path in O(N) time. A prototype machine with 64 processors has been developed to deal with a 128 multiplied by 128 grid plane. The architecture of the machine is discussed, together with its experimental performance data. The parallel processed Lee algorithm is most useful and powerful when applied to interactive rip-up and reroute.
AB - A parallel-processing architecture for hardware routers based on the Lee algorithm is presented. Unlike the existing machines, which require N**2 processors to implement the Lee algorithm on an N multiplied by N grid plane, the proposed architecture requires only O(N) processors to find a path in O(N) time. A prototype machine with 64 processors has been developed to deal with a 128 multiplied by 128 grid plane. The architecture of the machine is discussed, together with its experimental performance data. The parallel processed Lee algorithm is most useful and powerful when applied to interactive rip-up and reroute.
UR - http://www.scopus.com/inward/record.url?scp=0022795581&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=0022795581&partnerID=8YFLogxK
M3 - Article
AN - SCOPUS:0022795581
VL - CAD-5
JO - IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
JF - IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
SN - 0278-0070
IS - 4
ER -