TY - JOUR
T1 - Hierarchical intellectual property protection using partially-mergeable cores
AU - Iyengar, Vikram
AU - Date, Hiroshi
AU - Sugihara, Makoto
AU - Chakrabarty, Krishnendu
PY - 2001/11
Y1 - 2001/11
N2 - We present a new technique for hierarchical intellectual property (IP) protection using partially-mergeable cores. The proposed core partitioning technique guarantees 100% protection of critical-IP, while simplifying test generation for the logic that is merged with the system. Since critical-IP is tested using BIST, the controllability and observability of internal lines in the core are enhanced, and test application time is reduced. Case studies using the ISIT-DLX and Picojava processor cores demonstrate the applicability of our technique.
AB - We present a new technique for hierarchical intellectual property (IP) protection using partially-mergeable cores. The proposed core partitioning technique guarantees 100% protection of critical-IP, while simplifying test generation for the logic that is merged with the system. Since critical-IP is tested using BIST, the controllability and observability of internal lines in the core are enhanced, and test application time is reduced. Case studies using the ISIT-DLX and Picojava processor cores demonstrate the applicability of our technique.
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M3 - Article
AN - SCOPUS:0035518170
SN - 0916-8508
VL - E84-A
SP - 2632
EP - 2638
JO - IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
JF - IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
IS - 11
ER -