High-efficiency CMOS push-pull power amplifier with multilayer center-tapped transformer

Shingo Nakamura, Daisuke Kanemoto, Tomoki Sadakiyo, Haruichi Kanaya

研究成果: ジャーナルへの寄稿記事

2 引用 (Scopus)

抄録

This paper describes the design of a push-pull power amplifier (PA) with a center-tapped transformer for transmitter applications on the 5.2-GHz band using 0.18μm CMOS technology. The type of the proposed PA is based on a double-ended push-pull (DEPP) configuration. DEPP has a simple construction with only transistors and transformers. The PA has reverse-phased cascode-connected transistors. The proposed transformer has a multilayer structure and was designed using electromagnetic field simulation. To achieve high power added efficiency (PAE), we assumed the optimized output impedance technique with a tunable impedance antenna. The PA has 13.2 dB linearity gain, 14.9 dBm 1-dB compression point (P1dB), and 27.4% maximum PAE.

元の言語英語
ページ(範囲)384-386
ページ数3
ジャーナルIEEJ Transactions on Electrical and Electronic Engineering
11
発行部数3
DOI
出版物ステータス出版済み - 5 1 2016
外部発表Yes

Fingerprint

Power amplifiers
Multilayers
Transistors
Electromagnetic fields
Transmitters
Antennas

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering

これを引用

High-efficiency CMOS push-pull power amplifier with multilayer center-tapped transformer. / Nakamura, Shingo; Kanemoto, Daisuke; Sadakiyo, Tomoki; Kanaya, Haruichi.

:: IEEJ Transactions on Electrical and Electronic Engineering, 巻 11, 番号 3, 01.05.2016, p. 384-386.

研究成果: ジャーナルへの寄稿記事

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