High-Efficiency CMOS RF-to-DC Rectifier Based on Dynamic Threshold Reduction Technique for Wireless Charging Applications

Manal M. Mohamed, Ghazal A. Fahmy, Adel B. Abdel-Rahman, Ahmed Allam, Adel Barakat, Mohammed Abo-Zahhad, Hongting Jia, Ramesh K. Pokharel

研究成果: Contribution to journalArticle査読

16 被引用数 (Scopus)

抄録

This paper presents a high-efficiency CMOS rectifier based on an improved dynamic threshold reduction technique (DTR). The proposed DTR consists of a clamper circuit that biases the gates of pMOS diode switches through a capacitor and diode-connected pMOS transistor. The clamper is used to insert a negative dc level to the input RF signal; therefore, more negative RF signal can be obtained to bias the gates of the main rectifying pMOS devices during its conduction phase. This mechanism reduces the threshold voltage of the main pMOS transistors and increases their sensitivity to the RF input signal. The proposed rectifier is implemented in a 0.18-μm CMOS technology and tested. The measurement shows a peak power conversion efficiency of 86% and an output voltage of 0.52 V at an input power of-16.5 dBm and an input frequency of 402 MHz. The core area of chip excluding measurement pads is 0.024 mm2

本文言語英語
論文番号8443341
ページ(範囲)46826-46832
ページ数7
ジャーナルIEEE Access
6
DOI
出版ステータス出版済み - 8 21 2018

All Science Journal Classification (ASJC) codes

  • コンピュータ サイエンス(全般)
  • 材料科学(全般)
  • 工学(全般)

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