High-Efficiency CMOS RF-to-DC Rectifier Based on Dynamic Threshold Reduction Technique for Wireless Charging Applications

Manal M. Mohamed, Ghazal A. Fahmy, Adel B. Abdel-Rahman, Ahmed Allam, Adel Barakat, Mohammed Abo-Zahhad, Hongting Jia, Ramesh K. Pokharel

研究成果: ジャーナルへの寄稿記事

6 引用 (Scopus)

抄録

This paper presents a high-efficiency CMOS rectifier based on an improved dynamic threshold reduction technique (DTR). The proposed DTR consists of a clamper circuit that biases the gates of pMOS diode switches through a capacitor and diode-connected pMOS transistor. The clamper is used to insert a negative dc level to the input RF signal; therefore, more negative RF signal can be obtained to bias the gates of the main rectifying pMOS devices during its conduction phase. This mechanism reduces the threshold voltage of the main pMOS transistors and increases their sensitivity to the RF input signal. The proposed rectifier is implemented in a 0.18-μm CMOS technology and tested. The measurement shows a peak power conversion efficiency of 86% and an output voltage of 0.52 V at an input power of-16.5 dBm and an input frequency of 402 MHz. The core area of chip excluding measurement pads is 0.024 mm2

元の言語英語
記事番号8443341
ページ(範囲)46826-46832
ページ数7
ジャーナルIEEE Access
6
DOI
出版物ステータス出版済み - 8 21 2018

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Transistors
Diodes
Threshold voltage
Conversion efficiency
Capacitors
Switches
Networks (circuits)
Electric potential

All Science Journal Classification (ASJC) codes

  • Computer Science(all)
  • Materials Science(all)
  • Engineering(all)

これを引用

High-Efficiency CMOS RF-to-DC Rectifier Based on Dynamic Threshold Reduction Technique for Wireless Charging Applications. / Mohamed, Manal M.; Fahmy, Ghazal A.; Abdel-Rahman, Adel B.; Allam, Ahmed; Barakat, Adel; Abo-Zahhad, Mohammed; Jia, Hongting; Pokharel, Ramesh K.

:: IEEE Access, 巻 6, 8443341, 21.08.2018, p. 46826-46832.

研究成果: ジャーナルへの寄稿記事

Mohamed, MM, Fahmy, GA, Abdel-Rahman, AB, Allam, A, Barakat, A, Abo-Zahhad, M, Jia, H & Pokharel, RK 2018, 'High-Efficiency CMOS RF-to-DC Rectifier Based on Dynamic Threshold Reduction Technique for Wireless Charging Applications', IEEE Access, 巻. 6, 8443341, pp. 46826-46832. https://doi.org/10.1109/ACCESS.2018.2866457
Mohamed MM, Fahmy GA, Abdel-Rahman AB, Allam A, Barakat A, Abo-Zahhad M その他. High-Efficiency CMOS RF-to-DC Rectifier Based on Dynamic Threshold Reduction Technique for Wireless Charging Applications. IEEE Access. 2018 8 21;6:46826-46832. 8443341. https://doi.org/10.1109/ACCESS.2018.2866457
Mohamed, Manal M. ; Fahmy, Ghazal A. ; Abdel-Rahman, Adel B. ; Allam, Ahmed ; Barakat, Adel ; Abo-Zahhad, Mohammed ; Jia, Hongting ; Pokharel, Ramesh K. / High-Efficiency CMOS RF-to-DC Rectifier Based on Dynamic Threshold Reduction Technique for Wireless Charging Applications. :: IEEE Access. 2018 ; 巻 6. pp. 46826-46832.
@article{77587daee0af4a518bd014d2519de27f,
title = "High-Efficiency CMOS RF-to-DC Rectifier Based on Dynamic Threshold Reduction Technique for Wireless Charging Applications",
abstract = "This paper presents a high-efficiency CMOS rectifier based on an improved dynamic threshold reduction technique (DTR). The proposed DTR consists of a clamper circuit that biases the gates of pMOS diode switches through a capacitor and diode-connected pMOS transistor. The clamper is used to insert a negative dc level to the input RF signal; therefore, more negative RF signal can be obtained to bias the gates of the main rectifying pMOS devices during its conduction phase. This mechanism reduces the threshold voltage of the main pMOS transistors and increases their sensitivity to the RF input signal. The proposed rectifier is implemented in a 0.18-μm CMOS technology and tested. The measurement shows a peak power conversion efficiency of 86{\%} and an output voltage of 0.52 V at an input power of-16.5 dBm and an input frequency of 402 MHz. The core area of chip excluding measurement pads is 0.024 mm2",
author = "Mohamed, {Manal M.} and Fahmy, {Ghazal A.} and Abdel-Rahman, {Adel B.} and Ahmed Allam and Adel Barakat and Mohammed Abo-Zahhad and Hongting Jia and Pokharel, {Ramesh K.}",
year = "2018",
month = "8",
day = "21",
doi = "10.1109/ACCESS.2018.2866457",
language = "English",
volume = "6",
pages = "46826--46832",
journal = "IEEE Access",
issn = "2169-3536",
publisher = "Institute of Electrical and Electronics Engineers Inc.",

}

TY - JOUR

T1 - High-Efficiency CMOS RF-to-DC Rectifier Based on Dynamic Threshold Reduction Technique for Wireless Charging Applications

AU - Mohamed, Manal M.

AU - Fahmy, Ghazal A.

AU - Abdel-Rahman, Adel B.

AU - Allam, Ahmed

AU - Barakat, Adel

AU - Abo-Zahhad, Mohammed

AU - Jia, Hongting

AU - Pokharel, Ramesh K.

PY - 2018/8/21

Y1 - 2018/8/21

N2 - This paper presents a high-efficiency CMOS rectifier based on an improved dynamic threshold reduction technique (DTR). The proposed DTR consists of a clamper circuit that biases the gates of pMOS diode switches through a capacitor and diode-connected pMOS transistor. The clamper is used to insert a negative dc level to the input RF signal; therefore, more negative RF signal can be obtained to bias the gates of the main rectifying pMOS devices during its conduction phase. This mechanism reduces the threshold voltage of the main pMOS transistors and increases their sensitivity to the RF input signal. The proposed rectifier is implemented in a 0.18-μm CMOS technology and tested. The measurement shows a peak power conversion efficiency of 86% and an output voltage of 0.52 V at an input power of-16.5 dBm and an input frequency of 402 MHz. The core area of chip excluding measurement pads is 0.024 mm2

AB - This paper presents a high-efficiency CMOS rectifier based on an improved dynamic threshold reduction technique (DTR). The proposed DTR consists of a clamper circuit that biases the gates of pMOS diode switches through a capacitor and diode-connected pMOS transistor. The clamper is used to insert a negative dc level to the input RF signal; therefore, more negative RF signal can be obtained to bias the gates of the main rectifying pMOS devices during its conduction phase. This mechanism reduces the threshold voltage of the main pMOS transistors and increases their sensitivity to the RF input signal. The proposed rectifier is implemented in a 0.18-μm CMOS technology and tested. The measurement shows a peak power conversion efficiency of 86% and an output voltage of 0.52 V at an input power of-16.5 dBm and an input frequency of 402 MHz. The core area of chip excluding measurement pads is 0.024 mm2

UR - http://www.scopus.com/inward/record.url?scp=85052715787&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=85052715787&partnerID=8YFLogxK

U2 - 10.1109/ACCESS.2018.2866457

DO - 10.1109/ACCESS.2018.2866457

M3 - Article

AN - SCOPUS:85052715787

VL - 6

SP - 46826

EP - 46832

JO - IEEE Access

JF - IEEE Access

SN - 2169-3536

M1 - 8443341

ER -