High linearity technique for ultra-wideband low noise amplifier in 0.18 μm CMOS technology

A. I.A. Galal, Ramesh Pokharel, Haruichi Kanaya, K. Yoshida

研究成果: ジャーナルへの寄稿記事

12 引用 (Scopus)

抄録

A linearization technique for ultra-wideband low noise amplifier (UWB LNA) has been designed and fabricated in standard 0.18 μm CMOS technology. The proposed technique exploits the complementary characteristics of NMOS and PMOS to improve the linearity performance. A two-stage UWB LNA is optimized to achieve high linearity over the 3.1-10.6 GHz range. The first stage adopts inverter topology with resistive feedback to provide high linearity and wideband input matching, whereas the second stage is a cascode amplifier with series and shunt inductive peaking techniques to extend the bandwidth and achieve high gain simultaneously. The proposed UWB LNA exhibits a measured flat gain of 15 dB within the entire band, a minimum noise figure of 3.5 dB, and an IIP3 of 6.4 dBm while consuming 8 mA from a 1.8 V power supply. The total chip area is 0.39 mm2, including all pads. The measured input return loss is kept below -11 dB, and the output return loss is -8 dB, from 3.1 to 10.6 GHz.

元の言語英語
ページ(範囲)12-17
ページ数6
ジャーナルAEU - International Journal of Electronics and Communications
66
発行部数1
DOI
出版物ステータス出版済み - 1 1 2012

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Broadband amplifiers
Low noise amplifiers
Ultra-wideband (UWB)
Noise figure
Linearization
Topology
Feedback
Bandwidth

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering

これを引用

High linearity technique for ultra-wideband low noise amplifier in 0.18 μm CMOS technology. / Galal, A. I.A.; Pokharel, Ramesh; Kanaya, Haruichi; Yoshida, K.

:: AEU - International Journal of Electronics and Communications, 巻 66, 番号 1, 01.01.2012, p. 12-17.

研究成果: ジャーナルへの寄稿記事

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