In this paper, we propose logic simulation techniques using vector processors, or supercomputers with pipeline architecture, as a new approach to accelerating simulation speed. In order to use vector processors efficiently, we have to tune up the coding scheme or the basic algorithms to be suitable for vector processing. We developed three types of new simulation techniques for vector processing, which are dedicated for (1) zero-delay simulation of comhinational circuits, (2) zero-delay simulation of synchronous sequential circuits, and (3) simulation with delay consideration. The first two are based on the compiler-driven method and the last on the event-driven method. We implemented logic simulators based on the above techniques on the FACOM VP-100 and VP-200 at Kyoto University and on the HITAC S-810/20 at the University of Tokyo. The maximum performance is about 7.7 × 109 gate-evaluations per second for combinational circuit simulation, 1.4 × 109 gate-evaluations per second for sequential circuit simulation (on the VP-200), and 230 × 103 events per second for timing simulation (on the S-810/20). These results are comparable to the performance of hardware simulation engines. Moreover, our techniques are so straightforward that we can implement them on most of the recent vector processors without serious modifications.
|ジャーナル||IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems|
|出版ステータス||出版済み - 5 1987|
All Science Journal Classification (ASJC) codes
- コンピュータ グラフィックスおよびコンピュータ支援設計