### 抄録

A high-speed VLSI multiplication algorithm internally using redundant binary representation is proposed. In n bit binary integer multiplication, n partial products are first generated and then added up pairwise by means of a binary tree of redundant binary adders. Since parallel addition of two n-digitredundant binary numbers can be performed in a constant time independent of n without carry propagation, n bit multiplication can be performed in a time proportional to log2n. Thecomputation time is almost the same as that by a multiplier with a Wallace tree, in which three partial products will be converted into two, in contrast to our two-to-one conversion, and is much shorter than that by an array multiplier for longer operands. The number of computation elements of an n bit multiplier based on the algorithm is proportional to n2It is almost the same as those of conventional ones. Furthermore, since the multiplier has a regular cellular array structure similar to an array multiplier, it is suitable for VLSI implementation. Thus, the multiplier is excellent in both computation speed and regularity in layout. It can be implemented on a VLSI chip with an area proportional to n2log2n. The algorithm can be directly applied to both unsigned and 2's complement binary integer multiplication.

元の言語 | 英語 |
---|---|

ページ（範囲） | 789-796 |

ページ数 | 8 |

ジャーナル | IEEE Transactions on Computers |

巻 | C-34 |

発行部数 | 9 |

DOI | |

出版物ステータス | 出版済み - 1985 |

外部発表 | Yes |

### Fingerprint

### All Science Journal Classification (ASJC) codes

- Computational Theory and Mathematics
- Hardware and Architecture
- Software
- Theoretical Computer Science
- Electrical and Electronic Engineering

### これを引用

*IEEE Transactions on Computers*,

*C-34*(9), 789-796. https://doi.org/10.1109/TC.1985.1676634

**High-Speed VLSI Multiplication Algorithm with a Redundant Binary Addition Tree.** / Takagi, Naofumi; Yasuura, Hiroto; Yajima, Shuzo.

研究成果: ジャーナルへの寄稿 › 記事

*IEEE Transactions on Computers*, 巻. C-34, 番号 9, pp. 789-796. https://doi.org/10.1109/TC.1985.1676634

}

TY - JOUR

T1 - High-Speed VLSI Multiplication Algorithm with a Redundant Binary Addition Tree

AU - Takagi, Naofumi

AU - Yasuura, Hiroto

AU - Yajima, Shuzo

PY - 1985

Y1 - 1985

N2 - A high-speed VLSI multiplication algorithm internally using redundant binary representation is proposed. In n bit binary integer multiplication, n partial products are first generated and then added up pairwise by means of a binary tree of redundant binary adders. Since parallel addition of two n-digitredundant binary numbers can be performed in a constant time independent of n without carry propagation, n bit multiplication can be performed in a time proportional to log2n. Thecomputation time is almost the same as that by a multiplier with a Wallace tree, in which three partial products will be converted into two, in contrast to our two-to-one conversion, and is much shorter than that by an array multiplier for longer operands. The number of computation elements of an n bit multiplier based on the algorithm is proportional to n2It is almost the same as those of conventional ones. Furthermore, since the multiplier has a regular cellular array structure similar to an array multiplier, it is suitable for VLSI implementation. Thus, the multiplier is excellent in both computation speed and regularity in layout. It can be implemented on a VLSI chip with an area proportional to n2log2n. The algorithm can be directly applied to both unsigned and 2's complement binary integer multiplication.

AB - A high-speed VLSI multiplication algorithm internally using redundant binary representation is proposed. In n bit binary integer multiplication, n partial products are first generated and then added up pairwise by means of a binary tree of redundant binary adders. Since parallel addition of two n-digitredundant binary numbers can be performed in a constant time independent of n without carry propagation, n bit multiplication can be performed in a time proportional to log2n. Thecomputation time is almost the same as that by a multiplier with a Wallace tree, in which three partial products will be converted into two, in contrast to our two-to-one conversion, and is much shorter than that by an array multiplier for longer operands. The number of computation elements of an n bit multiplier based on the algorithm is proportional to n2It is almost the same as those of conventional ones. Furthermore, since the multiplier has a regular cellular array structure similar to an array multiplier, it is suitable for VLSI implementation. Thus, the multiplier is excellent in both computation speed and regularity in layout. It can be implemented on a VLSI chip with an area proportional to n2log2n. The algorithm can be directly applied to both unsigned and 2's complement binary integer multiplication.

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U2 - 10.1109/TC.1985.1676634

DO - 10.1109/TC.1985.1676634

M3 - Article

AN - SCOPUS:0022121184

VL - C-34

SP - 789

EP - 796

JO - IEEE Transactions on Computers

JF - IEEE Transactions on Computers

SN - 0018-9340

IS - 9

ER -