High-Speed VLSI Multiplication Algorithm with a Redundant Binary Addition Tree

Naofumi Takagi, Hiroto Yasuura, Shuzo Yajima

研究成果: Contribution to journalArticle査読

242 被引用数 (Scopus)

抄録

A high-speed VLSI multiplication algorithm internally using redundant binary representation is proposed. In n bit binary integer multiplication, n partial products are first generated and then added up pairwise by means of a binary tree of redundant binary adders. Since parallel addition of two n-digitredundant binary numbers can be performed in a constant time independent of n without carry propagation, n bit multiplication can be performed in a time proportional to log2n. Thecomputation time is almost the same as that by a multiplier with a Wallace tree, in which three partial products will be converted into two, in contrast to our two-to-one conversion, and is much shorter than that by an array multiplier for longer operands. The number of computation elements of an n bit multiplier based on the algorithm is proportional to n2It is almost the same as those of conventional ones. Furthermore, since the multiplier has a regular cellular array structure similar to an array multiplier, it is suitable for VLSI implementation. Thus, the multiplier is excellent in both computation speed and regularity in layout. It can be implemented on a VLSI chip with an area proportional to n2log2n. The algorithm can be directly applied to both unsigned and 2's complement binary integer multiplication.

本文言語英語
ページ(範囲)789-796
ページ数8
ジャーナルIEEE Transactions on Computers
C-34
9
DOI
出版ステータス出版済み - 1985
外部発表はい

All Science Journal Classification (ASJC) codes

  • 計算理論と計算数学
  • ハードウェアとアーキテクチャ
  • ソフトウェア
  • 理論的コンピュータサイエンス
  • 電子工学および電気工学

フィンガープリント

「High-Speed VLSI Multiplication Algorithm with a Redundant Binary Addition Tree」の研究トピックを掘り下げます。これらがまとまってユニークなフィンガープリントを構成します。

引用スタイル