This paper presents a novel technique to improve the quality factor (Q-factor) of a standard inductor in Si-substrate without post-processing. The proposed method employs a distributed grid of N-well in the P-substrate beneath the inductor. This will create a layer of PN junctions. The width of the N-well is chosen wisely so that full depletion occurs in every PN junction, forming a large depleted area which has high resistivity, thus reduces the substrate loss and increases Q-factor of the inductor. An example of the proposed idea is illustrated using a 1nH inductor in 0.18 μm CMOS technology. In this paper, High-Frequency Simulation Structure (HFSS)1) based on finite element method is used for simulation. As expected, the electromagnetic (EM) simulation shows that the total equivalent resistance of the inductor decreases, resulting in the improvement of its Q-factor by 9%. Finally, the improved inductor is used to design a 5GHz cross-coupled CMOS LC oscillator, which results in an improvement of 2.1dBc/Hz of phase noise at 10 kHz offset frequency.
|ジャーナル||Research Reports on Information Science and Electrical Engineering of Kyushu University|
|出版ステータス||出版済み - 7 1 2016|
All Science Journal Classification (ASJC) codes
- コンピュータ サイエンス（全般）