抄録
This paper proposes an instruction scheduling technique to reduce power consumed for off-chip driving. The technique minimizes the switching activity of a data bus between an on-chip cache and a main memory when instruction cache misses occur. The scheduling problem is formulated and a scheduling algorithm is also presented. Experimental results demonstrate the effectiveness and the efficiency of the proposed algorithm.
| 元の言語 | 英語 |
|---|---|
| 記事番号 | 655958 |
| ページ（範囲） | 855-860 |
| ページ数 | 6 |
| ジャーナル | Proceedings -Design, Automation and Test in Europe, DATE |
| DOI | |
| 出版物ステータス | 出版済み - 12 1 1998 |
| イベント | Design, Automation and Test in Europe, DATE 1998 - Paris, フランス 継続期間: 2 23 1998 → 2 26 1998 |
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All Science Journal Classification (ASJC) codes
- Engineering(all)
これを引用
Instruction scheduling for power reduction in processor-based system design. / Tomiyama, Hiroyuki; Ishihara, Tohru; Inoue, Akihiko; Yasuura, Hiroto.
：: Proceedings -Design, Automation and Test in Europe, DATE, 01.12.1998, p. 855-860.研究成果: ジャーナルへの寄稿 › Conference article
}
TY - JOUR
T1 - Instruction scheduling for power reduction in processor-based system design
AU - Tomiyama, Hiroyuki
AU - Ishihara, Tohru
AU - Inoue, Akihiko
AU - Yasuura, Hiroto
PY - 1998/12/1
Y1 - 1998/12/1
N2 - This paper proposes an instruction scheduling technique to reduce power consumed for off-chip driving. The technique minimizes the switching activity of a data bus between an on-chip cache and a main memory when instruction cache misses occur. The scheduling problem is formulated and a scheduling algorithm is also presented. Experimental results demonstrate the effectiveness and the efficiency of the proposed algorithm.
AB - This paper proposes an instruction scheduling technique to reduce power consumed for off-chip driving. The technique minimizes the switching activity of a data bus between an on-chip cache and a main memory when instruction cache misses occur. The scheduling problem is formulated and a scheduling algorithm is also presented. Experimental results demonstrate the effectiveness and the efficiency of the proposed algorithm.
UR - http://www.scopus.com/inward/record.url?scp=20444438621&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=20444438621&partnerID=8YFLogxK
U2 - 10.1109/DATE.1998.655958
DO - 10.1109/DATE.1998.655958
M3 - Conference article
AN - SCOPUS:20444438621
SP - 855
EP - 860
JO - Proceedings -Design, Automation and Test in Europe, DATE
JF - Proceedings -Design, Automation and Test in Europe, DATE
SN - 1530-1591
M1 - 655958
ER -