TY - JOUR
T1 - Instruction scheduling for power reduction in processor-based system design
AU - Tomiyama, Hiroyuki
AU - Ishihara, Tohru
AU - Inoue, Akihiko
AU - Yasuura, Hiroto
PY - 1998
Y1 - 1998
N2 - This paper proposes an instruction scheduling technique to reduce power consumed for off-chip driving. The technique minimizes the switching activity of a data bus between an on-chip cache and a main memory when instruction cache misses occur. The scheduling problem is formulated and a scheduling algorithm is also presented. Experimental results demonstrate the effectiveness and the efficiency of the proposed algorithm.
AB - This paper proposes an instruction scheduling technique to reduce power consumed for off-chip driving. The technique minimizes the switching activity of a data bus between an on-chip cache and a main memory when instruction cache misses occur. The scheduling problem is formulated and a scheduling algorithm is also presented. Experimental results demonstrate the effectiveness and the efficiency of the proposed algorithm.
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U2 - 10.1109/DATE.1998.655958
DO - 10.1109/DATE.1998.655958
M3 - Conference article
AN - SCOPUS:20444438621
SP - 855
EP - 860
JO - Proceedings -Design, Automation and Test in Europe, DATE
JF - Proceedings -Design, Automation and Test in Europe, DATE
SN - 1530-1591
M1 - 655958
T2 - Design, Automation and Test in Europe, DATE 1998
Y2 - 23 February 1998 through 26 February 1998
ER -