Instruction scheduling for power reduction in processor-based system design

Hiroyuki Tomiyama, Tohru Ishihara, Akihiko Inoue, Hiroto Yasuura

研究成果: Contribution to journalConference article査読

24 被引用数 (Scopus)

抄録

This paper proposes an instruction scheduling technique to reduce power consumed for off-chip driving. The technique minimizes the switching activity of a data bus between an on-chip cache and a main memory when instruction cache misses occur. The scheduling problem is formulated and a scheduling algorithm is also presented. Experimental results demonstrate the effectiveness and the efficiency of the proposed algorithm.

本文言語英語
論文番号655958
ページ(範囲)855-860
ページ数6
ジャーナルProceedings -Design, Automation and Test in Europe, DATE
DOI
出版ステータス出版済み - 1998
イベントDesign, Automation and Test in Europe, DATE 1998 - Paris, フランス
継続期間: 2 23 19982 26 1998

All Science Journal Classification (ASJC) codes

  • Engineering(all)

フィンガープリント 「Instruction scheduling for power reduction in processor-based system design」の研究トピックを掘り下げます。これらがまとまってユニークなフィンガープリントを構成します。

引用スタイル