Instruction scheduling to reduce switching activity of off-chip buses for low-power systems with caches

Hiroyuki Tomiyama, Tohru Ishihara, Akihiko Inoue, Hiroto Yasuura

研究成果: ジャーナルへの寄稿記事

5 引用 (Scopus)

抄録

In many embedded systems, a significant amount of power is consumed for off-chip driving because off-chip capacitances are much larger than on-chip capacitances. This paper proposes instruction scheduling techniques to reduce power consumed for off-chip driving. The techniques minimize the switching activity of a data bus between an on-chip cache and a main memory when instruction cache misses occur. The scheduling problem is formulated and two scheduling algorithms are presented. Experimental results demonstrate the effectiveness and the efficiency of the proposed algorithms.

元の言語英語
ページ(範囲)2621-2629
ページ数9
ジャーナルIEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
E81-A
発行部数12
出版物ステータス出版済み - 1 1 1998

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Instruction Scheduling
Power System
Cache
Chip
Capacitance
Scheduling
Scheduling algorithms
Embedded systems
Data storage equipment
Scheduling Algorithm
Embedded Systems
Scheduling Problem
Minimise
Experimental Results
Demonstrate

All Science Journal Classification (ASJC) codes

  • Signal Processing
  • Computer Graphics and Computer-Aided Design
  • Electrical and Electronic Engineering
  • Applied Mathematics

これを引用

Instruction scheduling to reduce switching activity of off-chip buses for low-power systems with caches. / Tomiyama, Hiroyuki; Ishihara, Tohru; Inoue, Akihiko; Yasuura, Hiroto.

:: IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, 巻 E81-A, 番号 12, 01.01.1998, p. 2621-2629.

研究成果: ジャーナルへの寄稿記事

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