抄録
In many embedded systems, a significant amount of power is consumed for off-chip driving because off-chip capacitances are much larger than on-chip capacitances. This paper proposes instruction scheduling techniques to reduce power consumed for off-chip driving. The techniques minimize the switching activity of a data bus between an on-chip cache and a main memory when instruction cache misses occur. The scheduling problem is formulated and two scheduling algorithms are presented. Experimental results demonstrate the effectiveness and the efficiency of the proposed algorithms.
| 元の言語 | 英語 |
|---|---|
| ページ（範囲） | 2621-2629 |
| ページ数 | 9 |
| ジャーナル | IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences |
| 巻 | E81-A |
| 発行部数 | 12 |
| 出版物ステータス | 出版済み - 1 1 1998 |
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All Science Journal Classification (ASJC) codes
- Signal Processing
- Computer Graphics and Computer-Aided Design
- Electrical and Electronic Engineering
- Applied Mathematics
これを引用
Instruction scheduling to reduce switching activity of off-chip buses for low-power systems with caches. / Tomiyama, Hiroyuki; Ishihara, Tohru; Inoue, Akihiko; Yasuura, Hiroto.
：: IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, 巻 E81-A, 番号 12, 01.01.1998, p. 2621-2629.研究成果: ジャーナルへの寄稿 › 記事
}
TY - JOUR
T1 - Instruction scheduling to reduce switching activity of off-chip buses for low-power systems with caches
AU - Tomiyama, Hiroyuki
AU - Ishihara, Tohru
AU - Inoue, Akihiko
AU - Yasuura, Hiroto
PY - 1998/1/1
Y1 - 1998/1/1
N2 - In many embedded systems, a significant amount of power is consumed for off-chip driving because off-chip capacitances are much larger than on-chip capacitances. This paper proposes instruction scheduling techniques to reduce power consumed for off-chip driving. The techniques minimize the switching activity of a data bus between an on-chip cache and a main memory when instruction cache misses occur. The scheduling problem is formulated and two scheduling algorithms are presented. Experimental results demonstrate the effectiveness and the efficiency of the proposed algorithms.
AB - In many embedded systems, a significant amount of power is consumed for off-chip driving because off-chip capacitances are much larger than on-chip capacitances. This paper proposes instruction scheduling techniques to reduce power consumed for off-chip driving. The techniques minimize the switching activity of a data bus between an on-chip cache and a main memory when instruction cache misses occur. The scheduling problem is formulated and two scheduling algorithms are presented. Experimental results demonstrate the effectiveness and the efficiency of the proposed algorithms.
UR - http://www.scopus.com/inward/record.url?scp=0032320587&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=0032320587&partnerID=8YFLogxK
M3 - Article
AN - SCOPUS:0032320587
VL - E81-A
SP - 2621
EP - 2629
JO - IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
JF - IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
SN - 0916-8508
IS - 12
ER -