Linearization technique using bipolar transistor at 5 GHz low noise amplifier

A. I.A. Galal, R. K. Pokharel, H. Kanaya, K. Yoshida

研究成果: Contribution to journalArticle

3 引用 (Scopus)

抜粋

A CMOS low noise amplifier (LNA) used in wireless communication systems, such as WLAN and CDMA, must have low noise figure, high linearity, and sufficient gain. Several techniques have been proposed to improve the linearity of CMOS LNA circuits. The proposed low noise amplifier achieves high third-order input intercept point (IIP3) using multi-gated configuration technique, by using two transistors, the first is the main CMOS transistor, and the second is bipolar transistor in TSMC 0.18 m technology. Bipolar transistor is used to cancel the third-order component from MOS transistor to fulfill high linearity operation. This work is designed and fabricated in TSMC 0.18 m CMOS process. At 5 GHz, the proposed LNA achieves a measurement results as 16 dBm of IIP3, 10.5 dB of gain, 2.1 dB of noise figure, and 8 mW of power consumption.

元の言語英語
ページ(範囲)978-982
ページ数5
ジャーナルAEU - International Journal of Electronics and Communications
64
発行部数10
DOI
出版物ステータス出版済み - 10 1 2010

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering

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