Logic BIST architecture using staggered launch-on-shift for testing designs containing asynchronous clock domains

Shianling Wu, Laung Terng Wang, Lizhen Yu, Hiroshi Furukawa, Xiaoqing Wen, Wen Ben Jone, Nur A. Touba, Feifei Zhao, Jinsong Liu, Hao Jan Chao, Fangfang Li, Zhigang Jiang

研究成果: Chapter in Book/Report/Conference proceedingConference contribution

9 被引用数 (Scopus)

抄録

This paper presents a new at-speed logic built-in self-test (BIST) architecture using staggered launch-on-shift (LOS) for testing a scan-based BIST design containing asynchronous clock domains. The proposed approach can detect inter-clock-domain structural faults and intra-clock-domain delay and structural faults in the BIST design. This solves the long-standing problem of using the conventional one-hot LOS approach that requires testing one clock domain at a time which causes long test time or using the simultaneous LOS approach that requires adding capture-disabled circuitry to normal functional paths across interacting clock domains which causes fault coverage loss. Given a fixed number of BIST patterns, experimental results showed that the proposed staggered clocking scheme can detect more faults than one-hot clocking and simultaneous clocking.

本文言語英語
ホスト出版物のタイトルProceedings - 2010 25th International Symposium on Defect and Fault Tolerance in VLSI Systems, DFT 2010
ページ358-366
ページ数9
DOI
出版ステータス出版済み - 12 1 2010
イベント2010 25th International Symposium on Defect and Fault Tolerance in VLSI Systems, DFT 2010 - Kyoto, 日本
継続期間: 10 6 201010 8 2010

出版物シリーズ

名前Proceedings - IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems
ISSN(印刷版)1550-5774

その他

その他2010 25th International Symposium on Defect and Fault Tolerance in VLSI Systems, DFT 2010
Country日本
CityKyoto
Period10/6/1010/8/10

All Science Journal Classification (ASJC) codes

  • Engineering(all)

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