This paper describes the slow wave structure design below the metallization plane to reduce dielectric loss of the silicon substrates. Three types of structure, floating strips with shield strip length (SL) = shield strip spacing (SS)=10μm and 5μm, and patterned ground with SL=SS=5μm have been designed for coplanar waveguide (CPW) transmission line using 0.18μm CMOS TSMC technology. These structures act to prevent the penetration of the electric field into the silicon substrate. It shows that at frequency of 60GHz, patterned ground shield resulted lower attenuation loss, approximately 60% lower compare to conventional CPW with the increase of quality factor to 16.006. The patterned structure exhibit the attenuation loss of 0.731dB/mm. The wavelength of the design is 980μm at 60GHz.