Module selection using manufacturing information

Hiroyuki Tomiyama, Hiroto Yasuura

研究成果: Contribution to conferencePaper査読

1 被引用数 (Scopus)

抄録

Since manufacturing processes inherently fluctuate, LSI chips which are produced from the same design have different propagation delays. However, the difference in delays caused by the the process fluctuation has rarely been considered in most high-level synthesis systems which were developed before. This paper presents a new approach to module selection in high-level synthesis, which exploits difference in functional unit delays. First, a module library model which assumes the probabilistic nature of functional unit delays is presented. Then, we propose a module selection problem and an algorithm which minimizes the cost per faultless chip. Experimental results demonstrate that the proposed algorithm finds the optimal module selection which would not have been explored without manufacturing information.

本文言語英語
ページ275-281
ページ数7
出版ステータス出版済み - 12 1 1998
イベントProceedings of the 1998 3rd Conference of the Asia and South Pacific Design Automation (ASP-DAC '98) - Yokohama, Jpn
継続期間: 2 10 19982 13 1998

会議

会議Proceedings of the 1998 3rd Conference of the Asia and South Pacific Design Automation (ASP-DAC '98)
CityYokohama, Jpn
Period2/10/982/13/98

All Science Journal Classification (ASJC) codes

  • コンピュータ サイエンスの応用
  • コンピュータ グラフィックスおよびコンピュータ支援設計
  • 電子工学および電気工学

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