Module selection using manufacturing information

Hiroyuki Tomiyama, Hiroto Yasuura

研究成果: ジャーナルへの寄稿学術誌査読

3 被引用数 (Scopus)

抄録

Since manufacturing processes inherently fluctuate, LSI chips which are produced from the same design have different propagation delays. However, the difference in delays caused by the process fluctuation has rarely been considered in most of existing high-level synthesis systems. This paper presents a new approach to module selection in high-level synthesis, which exploits the difference in functional unit delays. First, a module library model which assumes the probabilistic nature of functional unit delays is presented. Then, \ve propose a module selection problem and an algorithm which minimizes the cost per faultless chip. Experimental results demonstrate that the proposed algorithm finds optimal module selections which would not have been explored without manufacturing information.

本文言語英語
ページ(範囲)2576-2584
ページ数9
ジャーナルIEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
E81-A
12
出版ステータス出版済み - 1998
外部発表はい

!!!All Science Journal Classification (ASJC) codes

  • 信号処理
  • コンピュータ グラフィックスおよびコンピュータ支援設計
  • 電子工学および電気工学
  • 応用数学

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