抄録
Since manufacturing processes inherently fluctuate, LSI chips which are produced from the same design have different propagation delays. However, the difference in delays caused by the process fluctuation has rarely been considered in most of existing high-level synthesis systems. This paper presents a new approach to module selection in high-level synthesis, which exploits the difference in functional unit delays. First, a module library model which assumes the probabilistic nature of functional unit delays is presented. Then, \ve propose a module selection problem and an algorithm which minimizes the cost per faultless chip. Experimental results demonstrate that the proposed algorithm finds optimal module selections which would not have been explored without manufacturing information.
| 元の言語 | 英語 |
|---|---|
| ページ（範囲） | 2576-2584 |
| ページ数 | 9 |
| ジャーナル | IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences |
| 巻 | E81-A |
| 発行部数 | 12 |
| 出版物ステータス | 出版済み - 1 1 1998 |
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All Science Journal Classification (ASJC) codes
- Signal Processing
- Computer Graphics and Computer-Aided Design
- Electrical and Electronic Engineering
- Applied Mathematics
これを引用
Module selection using manufacturing information. / Tomiyama, Hiroyuki; Yasuura, Hiroto.
：: IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, 巻 E81-A, 番号 12, 01.01.1998, p. 2576-2584.研究成果: ジャーナルへの寄稿 › 記事
}
TY - JOUR
T1 - Module selection using manufacturing information
AU - Tomiyama, Hiroyuki
AU - Yasuura, Hiroto
PY - 1998/1/1
Y1 - 1998/1/1
N2 - Since manufacturing processes inherently fluctuate, LSI chips which are produced from the same design have different propagation delays. However, the difference in delays caused by the process fluctuation has rarely been considered in most of existing high-level synthesis systems. This paper presents a new approach to module selection in high-level synthesis, which exploits the difference in functional unit delays. First, a module library model which assumes the probabilistic nature of functional unit delays is presented. Then, \ve propose a module selection problem and an algorithm which minimizes the cost per faultless chip. Experimental results demonstrate that the proposed algorithm finds optimal module selections which would not have been explored without manufacturing information.
AB - Since manufacturing processes inherently fluctuate, LSI chips which are produced from the same design have different propagation delays. However, the difference in delays caused by the process fluctuation has rarely been considered in most of existing high-level synthesis systems. This paper presents a new approach to module selection in high-level synthesis, which exploits the difference in functional unit delays. First, a module library model which assumes the probabilistic nature of functional unit delays is presented. Then, \ve propose a module selection problem and an algorithm which minimizes the cost per faultless chip. Experimental results demonstrate that the proposed algorithm finds optimal module selections which would not have been explored without manufacturing information.
UR - http://www.scopus.com/inward/record.url?scp=0032318395&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=0032318395&partnerID=8YFLogxK
M3 - Article
VL - E81-A
SP - 2576
EP - 2584
JO - IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
JF - IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
SN - 0916-8508
IS - 12
ER -