Module selection using manufacturing information

Hiroyuki Tomiyama, Hiroto Yasuura

研究成果: ジャーナルへの寄稿記事

3 引用 (Scopus)

抄録

Since manufacturing processes inherently fluctuate, LSI chips which are produced from the same design have different propagation delays. However, the difference in delays caused by the process fluctuation has rarely been considered in most of existing high-level synthesis systems. This paper presents a new approach to module selection in high-level synthesis, which exploits the difference in functional unit delays. First, a module library model which assumes the probabilistic nature of functional unit delays is presented. Then, \ve propose a module selection problem and an algorithm which minimizes the cost per faultless chip. Experimental results demonstrate that the proposed algorithm finds optimal module selections which would not have been explored without manufacturing information.

元の言語英語
ページ(範囲)2576-2584
ページ数9
ジャーナルIEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
E81-A
発行部数12
出版物ステータス出版済み - 1 1 1998

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Manufacturing
High-level Synthesis
Module
Chip
Unit
Costs
Propagation
Fluctuations
Minimise
High level synthesis
Experimental Results
Demonstrate
Model

All Science Journal Classification (ASJC) codes

  • Signal Processing
  • Computer Graphics and Computer-Aided Design
  • Electrical and Electronic Engineering
  • Applied Mathematics

これを引用

Module selection using manufacturing information. / Tomiyama, Hiroyuki; Yasuura, Hiroto.

:: IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, 巻 E81-A, 番号 12, 01.01.1998, p. 2576-2584.

研究成果: ジャーナルへの寄稿記事

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