Multi-level logic minimization across latch boundaries

Yusuke Matsunaga, Masahiro Fujita, Taeko Kakuda

研究成果: Chapter in Book/Report/Conference proceedingConference contribution

3 被引用数 (Scopus)

抄録

A method to minimize sequential circuits is presented. It uses permissible functions extended for sequential circuits, and can make use of don't cares derived from network topology. Also, an efficient binary decision diagram (BDD) implementation of the extended permissible functions is presented by introducing edge attributes that indicate time label to the BDD. Circuits including latches can be efficiently minimized with the proposed method.

本文言語英語
ホスト出版物のタイトル1990 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers
出版社Publ by IEEE
ページ406-409
ページ数4
ISBN(印刷版)0818620552
出版ステータス出版済み - 12 1 1990
外部発表はい
イベント1990 IEEE International Conference on Computer-Aided Design - ICCAD-90 - Santa Clara, CA, USA
継続期間: 11 11 199011 15 1990

出版物シリーズ

名前1990 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers

その他

その他1990 IEEE International Conference on Computer-Aided Design - ICCAD-90
CitySanta Clara, CA, USA
Period11/11/9011/15/90

All Science Journal Classification (ASJC) codes

  • Engineering(all)

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引用スタイル