Multi-level logic minimization based on minimal support and its application to the minimization of look-up table type FPGAs

Masahiro Fujita, Yusuke Matsunaga

研究成果: 著書/レポートタイプへの貢献会議での発言

9 引用 (Scopus)

抄録

The authors present a method for multilevel logic minimization which is particularly suitable for the minimization of look-up table type FPGAs (field programmable gate arrays). Given a set of nodes to be minimized, one first calculates sets of supports which are necessary to construct the functions for the given nodes by applying functional reduction. The functional reduction process guarantees that one can get the minimal support for each node. One then makes a covering table for the set of nodes to be minimized so that one can get the minimal supports to cover all the functions for the given set of nodes to be minimized. The authors present a preliminary implementation and its results for ISCAS combinational benchmark circuits combined with MIS2.1 standard script and a Boolean resubstitution minimizer, and show the effectiveness of the presented method.

元の言語英語
ホスト出版物のタイトル1991 IEEE International Conference on Computer-Aided Design Digest of Technical Papers
出版者Publ by IEEE
ページ560-563
ページ数4
ISBN(印刷物)0818621575
出版物ステータス出版済み - 1992
外部発表Yes
イベント1991 IEEE International Conference on Computer-Aided Design - ICCAD-91 - Santa Clara, CA, USA
継続期間: 11 11 199111 14 1991

その他

その他1991 IEEE International Conference on Computer-Aided Design - ICCAD-91
Santa Clara, CA, USA
期間11/11/9111/14/91

Fingerprint

Field programmable gate arrays (FPGA)
Combinatorial circuits

All Science Journal Classification (ASJC) codes

  • Engineering(all)

これを引用

Fujita, M., & Matsunaga, Y. (1992). Multi-level logic minimization based on minimal support and its application to the minimization of look-up table type FPGAs. : 1991 IEEE International Conference on Computer-Aided Design Digest of Technical Papers (pp. 560-563). Publ by IEEE.

Multi-level logic minimization based on minimal support and its application to the minimization of look-up table type FPGAs. / Fujita, Masahiro; Matsunaga, Yusuke.

1991 IEEE International Conference on Computer-Aided Design Digest of Technical Papers. Publ by IEEE, 1992. p. 560-563.

研究成果: 著書/レポートタイプへの貢献会議での発言

Fujita, M & Matsunaga, Y 1992, Multi-level logic minimization based on minimal support and its application to the minimization of look-up table type FPGAs. : 1991 IEEE International Conference on Computer-Aided Design Digest of Technical Papers. Publ by IEEE, pp. 560-563, 1991 IEEE International Conference on Computer-Aided Design - ICCAD-91, Santa Clara, CA, USA, 11/11/91.
Fujita M, Matsunaga Y. Multi-level logic minimization based on minimal support and its application to the minimization of look-up table type FPGAs. : 1991 IEEE International Conference on Computer-Aided Design Digest of Technical Papers. Publ by IEEE. 1992. p. 560-563
Fujita, Masahiro ; Matsunaga, Yusuke. / Multi-level logic minimization based on minimal support and its application to the minimization of look-up table type FPGAs. 1991 IEEE International Conference on Computer-Aided Design Digest of Technical Papers. Publ by IEEE, 1992. pp. 560-563
@inproceedings{1ca567d880c340e8a3083e723674e5aa,
title = "Multi-level logic minimization based on minimal support and its application to the minimization of look-up table type FPGAs",
abstract = "The authors present a method for multilevel logic minimization which is particularly suitable for the minimization of look-up table type FPGAs (field programmable gate arrays). Given a set of nodes to be minimized, one first calculates sets of supports which are necessary to construct the functions for the given nodes by applying functional reduction. The functional reduction process guarantees that one can get the minimal support for each node. One then makes a covering table for the set of nodes to be minimized so that one can get the minimal supports to cover all the functions for the given set of nodes to be minimized. The authors present a preliminary implementation and its results for ISCAS combinational benchmark circuits combined with MIS2.1 standard script and a Boolean resubstitution minimizer, and show the effectiveness of the presented method.",
author = "Masahiro Fujita and Yusuke Matsunaga",
year = "1992",
language = "English",
isbn = "0818621575",
pages = "560--563",
booktitle = "1991 IEEE International Conference on Computer-Aided Design Digest of Technical Papers",
publisher = "Publ by IEEE",

}

TY - GEN

T1 - Multi-level logic minimization based on minimal support and its application to the minimization of look-up table type FPGAs

AU - Fujita, Masahiro

AU - Matsunaga, Yusuke

PY - 1992

Y1 - 1992

N2 - The authors present a method for multilevel logic minimization which is particularly suitable for the minimization of look-up table type FPGAs (field programmable gate arrays). Given a set of nodes to be minimized, one first calculates sets of supports which are necessary to construct the functions for the given nodes by applying functional reduction. The functional reduction process guarantees that one can get the minimal support for each node. One then makes a covering table for the set of nodes to be minimized so that one can get the minimal supports to cover all the functions for the given set of nodes to be minimized. The authors present a preliminary implementation and its results for ISCAS combinational benchmark circuits combined with MIS2.1 standard script and a Boolean resubstitution minimizer, and show the effectiveness of the presented method.

AB - The authors present a method for multilevel logic minimization which is particularly suitable for the minimization of look-up table type FPGAs (field programmable gate arrays). Given a set of nodes to be minimized, one first calculates sets of supports which are necessary to construct the functions for the given nodes by applying functional reduction. The functional reduction process guarantees that one can get the minimal support for each node. One then makes a covering table for the set of nodes to be minimized so that one can get the minimal supports to cover all the functions for the given set of nodes to be minimized. The authors present a preliminary implementation and its results for ISCAS combinational benchmark circuits combined with MIS2.1 standard script and a Boolean resubstitution minimizer, and show the effectiveness of the presented method.

UR - http://www.scopus.com/inward/record.url?scp=0027045913&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=0027045913&partnerID=8YFLogxK

M3 - Conference contribution

AN - SCOPUS:0027045913

SN - 0818621575

SP - 560

EP - 563

BT - 1991 IEEE International Conference on Computer-Aided Design Digest of Technical Papers

PB - Publ by IEEE

ER -