Multi-level logic minimization based on minimal support and its application to the minimization of look-up table type FPGAs

Masahiro Fujita, Yusuke Matsunaga

研究成果: Chapter in Book/Report/Conference proceedingConference contribution

9 被引用数 (Scopus)

抄録

The authors present a method for multilevel logic minimization which is particularly suitable for the minimization of look-up table type FPGAs (field programmable gate arrays). Given a set of nodes to be minimized, one first calculates sets of supports which are necessary to construct the functions for the given nodes by applying functional reduction. The functional reduction process guarantees that one can get the minimal support for each node. One then makes a covering table for the set of nodes to be minimized so that one can get the minimal supports to cover all the functions for the given set of nodes to be minimized. The authors present a preliminary implementation and its results for ISCAS combinational benchmark circuits combined with MIS2.1 standard script and a Boolean resubstitution minimizer, and show the effectiveness of the presented method.

本文言語英語
ホスト出版物のタイトル1991 IEEE International Conference on Computer-Aided Design Digest of Technical Papers
出版社Publ by IEEE
ページ560-563
ページ数4
ISBN(印刷版)0818621575
出版ステータス出版済み - 1992
外部発表はい
イベント1991 IEEE International Conference on Computer-Aided Design - ICCAD-91 - Santa Clara, CA, USA
継続期間: 11 11 199111 14 1991

その他

その他1991 IEEE International Conference on Computer-Aided Design - ICCAD-91
CitySanta Clara, CA, USA
Period11/11/9111/14/91

All Science Journal Classification (ASJC) codes

  • Engineering(all)

フィンガープリント 「Multi-level logic minimization based on minimal support and its application to the minimization of look-up table type FPGAs」の研究トピックを掘り下げます。これらがまとまってユニークなフィンガープリントを構成します。

引用スタイル