Multi-operand adder synthesis targeting FPGAs

Taeko Matsunaga, Shinji Kimura, Yusuke Matsunaga

研究成果: ジャーナルへの寄稿学術誌査読

11 被引用数 (Scopus)

抄録

Multi-operand adders, which calculates the summation of more than two operands, usually consist of compressor trees which reduce the number of operands to two without any carry propagation, and a carrypropagate adder for the two operands in ASIC implementation. The former part is usually realized using full adders or (3;2) counters likeWallace-trees in ASIC, while adder trees or dedicated hardware are used in FPGA. In this paper, an approach to realize compression trees on FPGAs is proposed. In case of FPGA with m-input LUT, any counters with up to m inputs can be realized with one LUT per an output. Our approach utilizes generalized parallel counters (GPCs) with up to m inputs and synthesizes highperformance compressor trees by setting some intermediate height limits in the compression process like Dadda's multipliers. Experimental results show that the number of GPCs are reduced by up to 22% compared to the existing heuristic. Its effectivity on reduction of delay is also shown against existing approaches on Altera's Stratix III.

本文言語英語
ページ(範囲)2579-2586
ページ数8
ジャーナルIEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
E94-A
12
DOI
出版ステータス出版済み - 12月 2011

!!!All Science Journal Classification (ASJC) codes

  • 信号処理
  • コンピュータ グラフィックスおよびコンピュータ支援設計
  • 電子工学および電気工学
  • 応用数学

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