Multiple-bit-upset and single-bit-upset resilient 8T SRAM bitcell layout with divided wordline structure

S. Yoshimoto, T. Amashita, D. Kozuwa, T. Takata, M. Yoshimura, Yusuke Matsunaga, Hiroto Yasuura, H. Kawaguchi, M. Yoshimoto

研究成果: 著書/レポートタイプへの貢献会議での発言

10 引用 (Scopus)

抄録

This paper presents a new 8T (8-transistor) SRAM cell layout mitigating multiple-bit upset (MBU) in a divided wordline structure. Because bitlines along unselected columns are not activated, the divided wordline structure eliminates a half-select problem and achieves low-power operation, which is often preferred for low-power / low-voltage applications. However, the conventional 8T SRAM with the divided wordline structure engenders MBUs because all bits in the same word are physically adjoining. Consequently, error correction coding (ECC) techniques are difficult to apply. This paper presents a new 8T cell layout pattern that separates internal latches in SRAM cells using both an n-well and a p-substrate. We investigated an SEU cross section of nMOS that is 3.5-4.5 times higher than that of pMOS. Using an iRoC TFIT simulator, we confirmed that the proposed 8T cell has better neutron-induced MBU tolerance. The MBU in the proposed 8T SRAM is improved by 90.70% and the MBU soft error rate (SER) is decreased to 3.46 FIT at 0.9 V when ECC is implemented. Additionally, we conducted Synopsys 3-D TCAD simulation, which indicates that the LET threshold (LETth) in single-event upset (SEU) is also improved by 66.47% in the proposed 8T SRAM by a common-mode effect.

元の言語英語
ホスト出版物のタイトルProceedings of the 2011 IEEE 17th International On-Line Testing Symposium, IOLTS 2011
ページ151-156
ページ数6
DOI
出版物ステータス出版済み - 9 19 2011
イベント2011 IEEE 17th International On-Line Testing Symposium, IOLTS 2011 - Athens, ギリシャ
継続期間: 7 13 20117 15 2011

出版物シリーズ

名前Proceedings of the 2011 IEEE 17th International On-Line Testing Symposium, IOLTS 2011

その他

その他2011 IEEE 17th International On-Line Testing Symposium, IOLTS 2011
ギリシャ
Athens
期間7/13/117/15/11

Fingerprint

Static random access storage
Transistors
Error correction
Neutrons
Simulators
Electric potential
Substrates

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering

これを引用

Yoshimoto, S., Amashita, T., Kozuwa, D., Takata, T., Yoshimura, M., Matsunaga, Y., ... Yoshimoto, M. (2011). Multiple-bit-upset and single-bit-upset resilient 8T SRAM bitcell layout with divided wordline structure. : Proceedings of the 2011 IEEE 17th International On-Line Testing Symposium, IOLTS 2011 (pp. 151-156). [5993829] (Proceedings of the 2011 IEEE 17th International On-Line Testing Symposium, IOLTS 2011). https://doi.org/10.1109/IOLTS.2011.5993829

Multiple-bit-upset and single-bit-upset resilient 8T SRAM bitcell layout with divided wordline structure. / Yoshimoto, S.; Amashita, T.; Kozuwa, D.; Takata, T.; Yoshimura, M.; Matsunaga, Yusuke; Yasuura, Hiroto; Kawaguchi, H.; Yoshimoto, M.

Proceedings of the 2011 IEEE 17th International On-Line Testing Symposium, IOLTS 2011. 2011. p. 151-156 5993829 (Proceedings of the 2011 IEEE 17th International On-Line Testing Symposium, IOLTS 2011).

研究成果: 著書/レポートタイプへの貢献会議での発言

Yoshimoto, S, Amashita, T, Kozuwa, D, Takata, T, Yoshimura, M, Matsunaga, Y, Yasuura, H, Kawaguchi, H & Yoshimoto, M 2011, Multiple-bit-upset and single-bit-upset resilient 8T SRAM bitcell layout with divided wordline structure. : Proceedings of the 2011 IEEE 17th International On-Line Testing Symposium, IOLTS 2011., 5993829, Proceedings of the 2011 IEEE 17th International On-Line Testing Symposium, IOLTS 2011, pp. 151-156, 2011 IEEE 17th International On-Line Testing Symposium, IOLTS 2011, Athens, ギリシャ, 7/13/11. https://doi.org/10.1109/IOLTS.2011.5993829
Yoshimoto S, Amashita T, Kozuwa D, Takata T, Yoshimura M, Matsunaga Y その他. Multiple-bit-upset and single-bit-upset resilient 8T SRAM bitcell layout with divided wordline structure. : Proceedings of the 2011 IEEE 17th International On-Line Testing Symposium, IOLTS 2011. 2011. p. 151-156. 5993829. (Proceedings of the 2011 IEEE 17th International On-Line Testing Symposium, IOLTS 2011). https://doi.org/10.1109/IOLTS.2011.5993829
Yoshimoto, S. ; Amashita, T. ; Kozuwa, D. ; Takata, T. ; Yoshimura, M. ; Matsunaga, Yusuke ; Yasuura, Hiroto ; Kawaguchi, H. ; Yoshimoto, M. / Multiple-bit-upset and single-bit-upset resilient 8T SRAM bitcell layout with divided wordline structure. Proceedings of the 2011 IEEE 17th International On-Line Testing Symposium, IOLTS 2011. 2011. pp. 151-156 (Proceedings of the 2011 IEEE 17th International On-Line Testing Symposium, IOLTS 2011).
@inproceedings{95316e54554743b28090fab0445318e1,
title = "Multiple-bit-upset and single-bit-upset resilient 8T SRAM bitcell layout with divided wordline structure",
abstract = "This paper presents a new 8T (8-transistor) SRAM cell layout mitigating multiple-bit upset (MBU) in a divided wordline structure. Because bitlines along unselected columns are not activated, the divided wordline structure eliminates a half-select problem and achieves low-power operation, which is often preferred for low-power / low-voltage applications. However, the conventional 8T SRAM with the divided wordline structure engenders MBUs because all bits in the same word are physically adjoining. Consequently, error correction coding (ECC) techniques are difficult to apply. This paper presents a new 8T cell layout pattern that separates internal latches in SRAM cells using both an n-well and a p-substrate. We investigated an SEU cross section of nMOS that is 3.5-4.5 times higher than that of pMOS. Using an iRoC TFIT simulator, we confirmed that the proposed 8T cell has better neutron-induced MBU tolerance. The MBU in the proposed 8T SRAM is improved by 90.70{\%} and the MBU soft error rate (SER) is decreased to 3.46 FIT at 0.9 V when ECC is implemented. Additionally, we conducted Synopsys 3-D TCAD simulation, which indicates that the LET threshold (LETth) in single-event upset (SEU) is also improved by 66.47{\%} in the proposed 8T SRAM by a common-mode effect.",
author = "S. Yoshimoto and T. Amashita and D. Kozuwa and T. Takata and M. Yoshimura and Yusuke Matsunaga and Hiroto Yasuura and H. Kawaguchi and M. Yoshimoto",
year = "2011",
month = "9",
day = "19",
doi = "10.1109/IOLTS.2011.5993829",
language = "English",
isbn = "9781457710551",
series = "Proceedings of the 2011 IEEE 17th International On-Line Testing Symposium, IOLTS 2011",
pages = "151--156",
booktitle = "Proceedings of the 2011 IEEE 17th International On-Line Testing Symposium, IOLTS 2011",

}

TY - GEN

T1 - Multiple-bit-upset and single-bit-upset resilient 8T SRAM bitcell layout with divided wordline structure

AU - Yoshimoto, S.

AU - Amashita, T.

AU - Kozuwa, D.

AU - Takata, T.

AU - Yoshimura, M.

AU - Matsunaga, Yusuke

AU - Yasuura, Hiroto

AU - Kawaguchi, H.

AU - Yoshimoto, M.

PY - 2011/9/19

Y1 - 2011/9/19

N2 - This paper presents a new 8T (8-transistor) SRAM cell layout mitigating multiple-bit upset (MBU) in a divided wordline structure. Because bitlines along unselected columns are not activated, the divided wordline structure eliminates a half-select problem and achieves low-power operation, which is often preferred for low-power / low-voltage applications. However, the conventional 8T SRAM with the divided wordline structure engenders MBUs because all bits in the same word are physically adjoining. Consequently, error correction coding (ECC) techniques are difficult to apply. This paper presents a new 8T cell layout pattern that separates internal latches in SRAM cells using both an n-well and a p-substrate. We investigated an SEU cross section of nMOS that is 3.5-4.5 times higher than that of pMOS. Using an iRoC TFIT simulator, we confirmed that the proposed 8T cell has better neutron-induced MBU tolerance. The MBU in the proposed 8T SRAM is improved by 90.70% and the MBU soft error rate (SER) is decreased to 3.46 FIT at 0.9 V when ECC is implemented. Additionally, we conducted Synopsys 3-D TCAD simulation, which indicates that the LET threshold (LETth) in single-event upset (SEU) is also improved by 66.47% in the proposed 8T SRAM by a common-mode effect.

AB - This paper presents a new 8T (8-transistor) SRAM cell layout mitigating multiple-bit upset (MBU) in a divided wordline structure. Because bitlines along unselected columns are not activated, the divided wordline structure eliminates a half-select problem and achieves low-power operation, which is often preferred for low-power / low-voltage applications. However, the conventional 8T SRAM with the divided wordline structure engenders MBUs because all bits in the same word are physically adjoining. Consequently, error correction coding (ECC) techniques are difficult to apply. This paper presents a new 8T cell layout pattern that separates internal latches in SRAM cells using both an n-well and a p-substrate. We investigated an SEU cross section of nMOS that is 3.5-4.5 times higher than that of pMOS. Using an iRoC TFIT simulator, we confirmed that the proposed 8T cell has better neutron-induced MBU tolerance. The MBU in the proposed 8T SRAM is improved by 90.70% and the MBU soft error rate (SER) is decreased to 3.46 FIT at 0.9 V when ECC is implemented. Additionally, we conducted Synopsys 3-D TCAD simulation, which indicates that the LET threshold (LETth) in single-event upset (SEU) is also improved by 66.47% in the proposed 8T SRAM by a common-mode effect.

UR - http://www.scopus.com/inward/record.url?scp=80052737344&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=80052737344&partnerID=8YFLogxK

U2 - 10.1109/IOLTS.2011.5993829

DO - 10.1109/IOLTS.2011.5993829

M3 - Conference contribution

SN - 9781457710551

T3 - Proceedings of the 2011 IEEE 17th International On-Line Testing Symposium, IOLTS 2011

SP - 151

EP - 156

BT - Proceedings of the 2011 IEEE 17th International On-Line Testing Symposium, IOLTS 2011

ER -