Multiplier energy reduction through bypassing of partial products

Jun Ni Ohban, V. G. Moshnyaga, K. Inoue

研究成果: Chapter in Book/Report/Conference proceedingConference contribution

57 被引用数 (Scopus)

抄録

The design of portable battery operated multimedia devices requires energy-efficient multiplication circuits. This paper presents a novel approach to reduce power consumption of digital multiplier based on dynamic bypassing of partial products. The bypassing elements incorporated into the multiplier hardware eliminate redundant signal transitions, which appear within the carry-save adders when the partial product is zero. Simulations on the real-life DCT data show that the proposed approach can improve power saving of related methods by 12%, while jointly with them, it reduces the power consumption of a 16x16 digital CMOS multiplier by 31%, with 25% area overhead and less than 4% performance degradation in the worst case. The circuit implementation is outlined.

本文言語英語
ホスト出版物のタイトルProceedings - APCCAS 2002
ホスト出版物のサブタイトルAsia-Pacific Conference on Circuits and Systems
出版社Institute of Electrical and Electronics Engineers Inc.
ページ13-17
ページ数5
ISBN(電子版)0780376900
DOI
出版ステータス出版済み - 1 1 2002
外部発表はい
イベントAsia-Pacific Conference on Circuits and Systems, APCCAS 2002 - Denpasar, Bali, インドネシア
継続期間: 10 28 200210 31 2002

出版物シリーズ

名前IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS
2

その他

その他Asia-Pacific Conference on Circuits and Systems, APCCAS 2002
国/地域インドネシア
CityDenpasar, Bali
Period10/28/0210/31/02

All Science Journal Classification (ASJC) codes

  • 電子工学および電気工学

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