Neutron-induced soft error rate estimation for SRAM using PHITS

Shusuke Yoshimoto, Takuro Amashita, Masayoshi Yoshimura, Yusuke Matsunaga, Hiroto Yasuura, Shintaro Izumi, Hiroshi Kawaguchi, Masahiko Yoshimoto

研究成果: 著書/レポートタイプへの貢献会議での発言

6 引用 (Scopus)

抄録

This paper presents a novel neutron-induced soft-error-rate (SER) estimation tool with a particle transport code: PHITS. The proposed tool can calculate the SER according to various data patterns and the layout of the memory cells in an SRAM. As layouts, two kinds of an NMOS-PMOS-NMOS 6T and an inside-out PMOS-NMOS-PMOS versions are considered. The proposed tool distinguishes a single-event-upset (SEU) SER, a horizontal multiple-cell-upset (MCU) SER, and a vertical MCU SER using an extracting function. The horizontal MCU SER in the inside-out version of the PMOS-NMOS-PMOS 6T SRAM cell layout was expected to be 26-41% less than that of the general NMOS-PMOS-NMOS 6T cell layout.

元の言語英語
ホスト出版物のタイトルProceedings of the 2012 IEEE 18th International On-Line Testing Symposium, IOLTS 2012
ページ138-141
ページ数4
DOI
出版物ステータス出版済み - 11 22 2012
イベント2012 IEEE 18th International On-Line Testing Symposium, IOLTS 2012 - Sitges, スペイン
継続期間: 6 27 20126 29 2012

出版物シリーズ

名前Proceedings of the 2012 IEEE 18th International On-Line Testing Symposium, IOLTS 2012

その他

その他2012 IEEE 18th International On-Line Testing Symposium, IOLTS 2012
スペイン
Sitges
期間6/27/126/29/12

Fingerprint

Static random access storage
Neutrons
Data storage equipment

All Science Journal Classification (ASJC) codes

  • Safety, Risk, Reliability and Quality

これを引用

Yoshimoto, S., Amashita, T., Yoshimura, M., Matsunaga, Y., Yasuura, H., Izumi, S., ... Yoshimoto, M. (2012). Neutron-induced soft error rate estimation for SRAM using PHITS. : Proceedings of the 2012 IEEE 18th International On-Line Testing Symposium, IOLTS 2012 (pp. 138-141). [6313859] (Proceedings of the 2012 IEEE 18th International On-Line Testing Symposium, IOLTS 2012). https://doi.org/10.1109/IOLTS.2012.6313859

Neutron-induced soft error rate estimation for SRAM using PHITS. / Yoshimoto, Shusuke; Amashita, Takuro; Yoshimura, Masayoshi; Matsunaga, Yusuke; Yasuura, Hiroto; Izumi, Shintaro; Kawaguchi, Hiroshi; Yoshimoto, Masahiko.

Proceedings of the 2012 IEEE 18th International On-Line Testing Symposium, IOLTS 2012. 2012. p. 138-141 6313859 (Proceedings of the 2012 IEEE 18th International On-Line Testing Symposium, IOLTS 2012).

研究成果: 著書/レポートタイプへの貢献会議での発言

Yoshimoto, S, Amashita, T, Yoshimura, M, Matsunaga, Y, Yasuura, H, Izumi, S, Kawaguchi, H & Yoshimoto, M 2012, Neutron-induced soft error rate estimation for SRAM using PHITS. : Proceedings of the 2012 IEEE 18th International On-Line Testing Symposium, IOLTS 2012., 6313859, Proceedings of the 2012 IEEE 18th International On-Line Testing Symposium, IOLTS 2012, pp. 138-141, 2012 IEEE 18th International On-Line Testing Symposium, IOLTS 2012, Sitges, スペイン, 6/27/12. https://doi.org/10.1109/IOLTS.2012.6313859
Yoshimoto S, Amashita T, Yoshimura M, Matsunaga Y, Yasuura H, Izumi S その他. Neutron-induced soft error rate estimation for SRAM using PHITS. : Proceedings of the 2012 IEEE 18th International On-Line Testing Symposium, IOLTS 2012. 2012. p. 138-141. 6313859. (Proceedings of the 2012 IEEE 18th International On-Line Testing Symposium, IOLTS 2012). https://doi.org/10.1109/IOLTS.2012.6313859
Yoshimoto, Shusuke ; Amashita, Takuro ; Yoshimura, Masayoshi ; Matsunaga, Yusuke ; Yasuura, Hiroto ; Izumi, Shintaro ; Kawaguchi, Hiroshi ; Yoshimoto, Masahiko. / Neutron-induced soft error rate estimation for SRAM using PHITS. Proceedings of the 2012 IEEE 18th International On-Line Testing Symposium, IOLTS 2012. 2012. pp. 138-141 (Proceedings of the 2012 IEEE 18th International On-Line Testing Symposium, IOLTS 2012).
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abstract = "This paper presents a novel neutron-induced soft-error-rate (SER) estimation tool with a particle transport code: PHITS. The proposed tool can calculate the SER according to various data patterns and the layout of the memory cells in an SRAM. As layouts, two kinds of an NMOS-PMOS-NMOS 6T and an inside-out PMOS-NMOS-PMOS versions are considered. The proposed tool distinguishes a single-event-upset (SEU) SER, a horizontal multiple-cell-upset (MCU) SER, and a vertical MCU SER using an extracting function. The horizontal MCU SER in the inside-out version of the PMOS-NMOS-PMOS 6T SRAM cell layout was expected to be 26-41{\%} less than that of the general NMOS-PMOS-NMOS 6T cell layout.",
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