Novel test methodology for core-based system LSIs and a testing time minimization problem

Makoto Sugihara; Hiroshi Date; Hiroto Yasuura

doi:10.1109/TEST.1998.743187

Novel test methodology for core-based system LSIs and a testing time minimization problem

Makoto Sugihara, Hiroshi Date, Hiroto Yasuura

研究成果: 書籍/レポートタイプへの寄稿 › 会議への寄与

26 被引用数 (Scopus)

抄録

In this paper, we propose a novel test methodology for core-based system LSIs. Our test methodology aims to decrease testing time for core-based system LSIs. Considering testing time reduction, our test methodology is based on BIST and ATPG. The main contributions of this paper are summarized as follows. (i). BIST is efficiently combined with external testing to relax the limitation of the external primary inputs and outputs. (ii). External testing for one of cores and BISTs for the others are performed in parallel to reduce the total testing time. (iii). The testing time minimization problem for core-based system LSIs is formulated as a combinatorial optimization problem to select the optimal set of test vectors from given sets of test vectors for each core.

本文言語	英語
ホスト出版物のタイトル	IEEE International Test Conference (TC)
編集者	Anon
ページ	465-472
ページ数	8
DOI	https://doi.org/10.1109/TEST.1998.743187
出版ステータス	出版済み - 12月 1 1998
イベント	Proceedings of the 1998 IEEE International Test Conference - Washington, DC, USA 継続期間: 10月 18 1998 → 10月 21 1998

出版物シリーズ

名前	IEEE International Test Conference (TC)
ISSN（印刷版）	1089-3539

その他

その他	Proceedings of the 1998 IEEE International Test Conference
City	Washington, DC, USA
Period	10/18/98 → 10/21/98

!!!All Science Journal Classification (ASJC) codes

電子工学および電気工学
応用数学

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10.1109/TEST.1998.743187

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引用スタイル

Sugihara, M, Date, H & Yasuura, H 1998, Novel test methodology for core-based system LSIs and a testing time minimization problem. in Anon (ed.), IEEE International Test Conference (TC). IEEE International Test Conference (TC), pp. 465-472, Proceedings of the 1998 IEEE International Test Conference, Washington, DC, USA, 10/18/98. https://doi.org/10.1109/TEST.1998.743187

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abstract = "In this paper, we propose a novel test methodology for core-based system LSIs. Our test methodology aims to decrease testing time for core-based system LSIs. Considering testing time reduction, our test methodology is based on BIST and ATPG. The main contributions of this paper are summarized as follows. (i). BIST is efficiently combined with external testing to relax the limitation of the external primary inputs and outputs. (ii). External testing for one of cores and BISTs for the others are performed in parallel to reduce the total testing time. (iii). The testing time minimization problem for core-based system LSIs is formulated as a combinatorial optimization problem to select the optimal set of test vectors from given sets of test vectors for each core.",

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N2 - In this paper, we propose a novel test methodology for core-based system LSIs. Our test methodology aims to decrease testing time for core-based system LSIs. Considering testing time reduction, our test methodology is based on BIST and ATPG. The main contributions of this paper are summarized as follows. (i). BIST is efficiently combined with external testing to relax the limitation of the external primary inputs and outputs. (ii). External testing for one of cores and BISTs for the others are performed in parallel to reduce the total testing time. (iii). The testing time minimization problem for core-based system LSIs is formulated as a combinatorial optimization problem to select the optimal set of test vectors from given sets of test vectors for each core.

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Novel test methodology for core-based system LSIs and a testing time minimization problem

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出版物シリーズ

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!!!All Science Journal Classification (ASJC) codes

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