On improvements of a SAT-solver PCMGTP on FPGA

Hiroshi Fujita, Ryuzo Hasegawa, Miyuki Koshimura, Shohei Kinoshita, Jun'ichi Matsuda

研究成果: Contribution to journalArticle査読

抄録

In this paper, an improved design of a SAT-solver PCMGTP on FPGA is described. The previous implementation of PCMGTP achieved considerable speedup of SAT-solving compared to the software counterpart of MGTP. After intensive analyses and experiments, it turned out that the early design contains much redundancy and has room for improvement. Also, we developed a generic description style in Verilog using arrays and iterative constructs. Experimental results show that the new implementation outperforms the old one with regard to both execution time and circuit size.

本文言語英語
ページ(範囲)21-26
ページ数6
ジャーナルResearch Reports on Information Science and Electrical Engineering of Kyushu University
10
1
出版ステータス出版済み - 3 1 2005

All Science Journal Classification (ASJC) codes

  • コンピュータ サイエンス(全般)
  • 電子工学および電気工学

フィンガープリント

「On improvements of a SAT-solver PCMGTP on FPGA」の研究トピックを掘り下げます。これらがまとまってユニークなフィンガープリントを構成します。

引用スタイル