This paper presents a three-phase four-leg-based split-source inverter (SSI) topology to reduce its instantaneous common-mode (CM) voltage. The proposed topology utilizes a simple discontinuous pulse width modulation (DPWM) strategy based on imaginary switching times (ISTs) with a single Boolean logic gate to drive the fourth leg. The paper first presents a brief analysis of the CM voltage issue in the available SSI equipped with different control techniques. Then, the principle of operation and the analysis of the proposed four-leg-based SSI topology along with the proposed modulation technique are introduced. Moreover, the output filter inductance's effect on the CM voltage levels is examined and the results are provided. To verify the effectiveness and demonstrate the performance of the proposed inverter topology with the associated modulation strategy, a Simulink model has been designed, evaluated and then verified with experiments with different case studies and modulation strategies. The obtained results show that the proposed four-leg-based SSI with the proposed modulation strategy not only restrains the instantaneous peak-to-peak CM voltage but also reduces the number of switching transitions in the resultant CM voltage.
|ジャーナル||International Journal of Electrical Power and Energy Systems|
|出版ステータス||出版済み - 5 2021|
All Science Journal Classification (ASJC) codes