In the realization of large-scale logic circuits as VLSI circuits, it is necessary to take into account the scale of the circuits from the logic design stage to the layout during the design process. Techniques in VLSI are being established, using a measure of 'area', gathering the elements, wires, terminals, etc. , together. Under the condition that the I/O ports of a circuit are located on the boundary of the convex region in which the circuit is embedded, this paper proposes a method to estimate the minimal area required in embedding the given logic circuit. For special circuits, such as tree circuits and square-grid or cubic-grid circuits, the lower bounds of the area required in their embeddings are shown. Particularly for the tree circuits, a new measure, called an effective height, is introduced and it is shown that theta (nh) is the lower bound of the area required in embedding the circuit with n I/O ports and effective height h. Moreover, lower bounds for trade-off between the area and computing time (number of stages) are shown for the case where n-variable logic circuits are to be computed using combinational logic circuits.
|ジャーナル||Systems, computers, controls|
|出版物ステータス||出版済み - 1 1 1982|
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