On variable ordering of binary decision diagrams for the application of multi-level logic synthesis

Masahiro Fujita, Yusuke Matsunaga, Taeko Kakuda

研究成果: Chapter in Book/Report/Conference proceedingConference contribution

98 被引用数 (Scopus)

抄録

We have developed multi-level logic minimization programs using Binary Decision Diagram (BDD). Here we present variable ordering methods of BDD. The variable ordering algorithm for two-level circuits is based on cover patterns and selects most binate variables first, and the one for multi-level circuits is based on depth first traverse of circuits. In both cases, the acquired variable orderings are optimized by exchanging a variable with its neighbor in the ordering.

本文言語英語
ホスト出版物のタイトルProc Eur Conf Des Autom
出版社Publ by IEEE
ページ50-54
ページ数5
ISBN(印刷版)0818626453
出版ステータス出版済み - 12 1 1992
外部発表はい
イベントProceedings the European Conference on Design Automation - Amsterdam, Neth
継続期間: 3 16 19923 19 1992

出版物シリーズ

名前Proc Eur Conf Des Autom

その他

その他Proceedings the European Conference on Design Automation
CityAmsterdam, Neth
Period3/16/923/19/92

All Science Journal Classification (ASJC) codes

  • Engineering(all)

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