On variable ordering of binary decision diagrams for the application of multi-level logic synthesis

Masahiro Fujita, Yusuke Matsunaga, Taeko Kakuda

研究成果: 著書/レポートタイプへの貢献会議での発言

97 引用 (Scopus)

抄録

We have developed multi-level logic minimization programs using Binary Decision Diagram (BDD). Here we present variable ordering methods of BDD. The variable ordering algorithm for two-level circuits is based on cover patterns and selects most binate variables first, and the one for multi-level circuits is based on depth first traverse of circuits. In both cases, the acquired variable orderings are optimized by exchanging a variable with its neighbor in the ordering.

元の言語英語
ホスト出版物のタイトルProc Eur Conf Des Autom
出版者Publ by IEEE
ページ50-54
ページ数5
ISBN(印刷物)0818626453
出版物ステータス出版済み - 12 1 1992
外部発表Yes
イベントProceedings the European Conference on Design Automation - Amsterdam, Neth
継続期間: 3 16 19923 19 1992

出版物シリーズ

名前Proc Eur Conf Des Autom

その他

その他Proceedings the European Conference on Design Automation
Amsterdam, Neth
期間3/16/923/19/92

Fingerprint

Binary decision diagrams
Networks (circuits)
Logic Synthesis

All Science Journal Classification (ASJC) codes

  • Engineering(all)

これを引用

Fujita, M., Matsunaga, Y., & Kakuda, T. (1992). On variable ordering of binary decision diagrams for the application of multi-level logic synthesis. : Proc Eur Conf Des Autom (pp. 50-54). (Proc Eur Conf Des Autom). Publ by IEEE.

On variable ordering of binary decision diagrams for the application of multi-level logic synthesis. / Fujita, Masahiro; Matsunaga, Yusuke; Kakuda, Taeko.

Proc Eur Conf Des Autom. Publ by IEEE, 1992. p. 50-54 (Proc Eur Conf Des Autom).

研究成果: 著書/レポートタイプへの貢献会議での発言

Fujita, M, Matsunaga, Y & Kakuda, T 1992, On variable ordering of binary decision diagrams for the application of multi-level logic synthesis. : Proc Eur Conf Des Autom. Proc Eur Conf Des Autom, Publ by IEEE, pp. 50-54, Proceedings the European Conference on Design Automation, Amsterdam, Neth, 3/16/92.
Fujita M, Matsunaga Y, Kakuda T. On variable ordering of binary decision diagrams for the application of multi-level logic synthesis. : Proc Eur Conf Des Autom. Publ by IEEE. 1992. p. 50-54. (Proc Eur Conf Des Autom).
Fujita, Masahiro ; Matsunaga, Yusuke ; Kakuda, Taeko. / On variable ordering of binary decision diagrams for the application of multi-level logic synthesis. Proc Eur Conf Des Autom. Publ by IEEE, 1992. pp. 50-54 (Proc Eur Conf Des Autom).
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