Optimization of test accesses with a combined BIST and external test scheme

Makoto Sugihara, Hiroto Yasuura

研究成果: 著書/レポートタイプへの貢献会議での発言

2 引用 (Scopus)

抄録

The proposed optimization method of test accesses, with a combined BIST and external test (CBET) scheme, can minimize the test time and eliminate the wasteful usage of external pins by considering the trade-off between test time and the number of external pins. Our idea consists of two parts. One is to determine the optimum groups, each of which consists of cores, to simultaneously share mechanisms for the external test. The other is to determine the optimum bandwidth of the external input and output for the external test. We design the external test part to be under the full bandwidth of external pins by considering the trade-off between the test time and the number of external pins. This is achieved only with the CBET scheme because it permits test sets for both the BIST and the external test to be elastic. Taking the test bus architecture as an example, a formulation for test access optimization and experimental results are shown. Experimental results reveal that our optimization can achieve a 51.9% reduction in the test time of conventional test scheduling and our proposals are confirmed to be effective in reducing the test time of system-on-a-chip.

元の言語英語
ホスト出版物のタイトルProceedings - 7th Asia and South Pacific Design Automation Conference, 15th International Conference on VLSI Design, ASP-DAC/VLSI Design 2002
出版者Institute of Electrical and Electronics Engineers Inc.
ページ683-688
ページ数6
ISBN(電子版)0769514413, 9780769514413
DOI
出版物ステータス出版済み - 1 1 2002
イベント7th Asia and South Pacific Design Automation Conference, 15th International Conference on VLSI Design, ASP-DAC/VLSI Design 2002 - Bangalore, インド
継続期間: 1 7 20021 11 2002

出版物シリーズ

名前Proceedings - 7th Asia and South Pacific Design Automation Conference, 15th International Conference on VLSI Design, ASP-DAC/VLSI Design 2002

その他

その他7th Asia and South Pacific Design Automation Conference, 15th International Conference on VLSI Design, ASP-DAC/VLSI Design 2002
インド
Bangalore
期間1/7/021/11/02

Fingerprint

Built-in self test
Bandwidth
Scheduling

All Science Journal Classification (ASJC) codes

  • Computer Graphics and Computer-Aided Design
  • Hardware and Architecture
  • Electrical and Electronic Engineering

これを引用

Sugihara, M., & Yasuura, H. (2002). Optimization of test accesses with a combined BIST and external test scheme. : Proceedings - 7th Asia and South Pacific Design Automation Conference, 15th International Conference on VLSI Design, ASP-DAC/VLSI Design 2002 (pp. 683-688). [995014] (Proceedings - 7th Asia and South Pacific Design Automation Conference, 15th International Conference on VLSI Design, ASP-DAC/VLSI Design 2002). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ASPDAC.2002.995014

Optimization of test accesses with a combined BIST and external test scheme. / Sugihara, Makoto; Yasuura, Hiroto.

Proceedings - 7th Asia and South Pacific Design Automation Conference, 15th International Conference on VLSI Design, ASP-DAC/VLSI Design 2002. Institute of Electrical and Electronics Engineers Inc., 2002. p. 683-688 995014 (Proceedings - 7th Asia and South Pacific Design Automation Conference, 15th International Conference on VLSI Design, ASP-DAC/VLSI Design 2002).

研究成果: 著書/レポートタイプへの貢献会議での発言

Sugihara, M & Yasuura, H 2002, Optimization of test accesses with a combined BIST and external test scheme. : Proceedings - 7th Asia and South Pacific Design Automation Conference, 15th International Conference on VLSI Design, ASP-DAC/VLSI Design 2002., 995014, Proceedings - 7th Asia and South Pacific Design Automation Conference, 15th International Conference on VLSI Design, ASP-DAC/VLSI Design 2002, Institute of Electrical and Electronics Engineers Inc., pp. 683-688, 7th Asia and South Pacific Design Automation Conference, 15th International Conference on VLSI Design, ASP-DAC/VLSI Design 2002, Bangalore, インド, 1/7/02. https://doi.org/10.1109/ASPDAC.2002.995014
Sugihara M, Yasuura H. Optimization of test accesses with a combined BIST and external test scheme. : Proceedings - 7th Asia and South Pacific Design Automation Conference, 15th International Conference on VLSI Design, ASP-DAC/VLSI Design 2002. Institute of Electrical and Electronics Engineers Inc. 2002. p. 683-688. 995014. (Proceedings - 7th Asia and South Pacific Design Automation Conference, 15th International Conference on VLSI Design, ASP-DAC/VLSI Design 2002). https://doi.org/10.1109/ASPDAC.2002.995014
Sugihara, Makoto ; Yasuura, Hiroto. / Optimization of test accesses with a combined BIST and external test scheme. Proceedings - 7th Asia and South Pacific Design Automation Conference, 15th International Conference on VLSI Design, ASP-DAC/VLSI Design 2002. Institute of Electrical and Electronics Engineers Inc., 2002. pp. 683-688 (Proceedings - 7th Asia and South Pacific Design Automation Conference, 15th International Conference on VLSI Design, ASP-DAC/VLSI Design 2002).
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