Parallel exhaustive search for several np-complete problems using content addressable memories

Hiroto Yasuura, Taizo Tsujimoto, Keikichi Tamaru

研究成果: 著書/レポートタイプへの貢献会議での発言

3 引用 (Scopus)

抜粋

The authors propose a simple parallel algorithm design technique for several NP-complete problems called parallel exhaustive search. Algorithms can be implemented on an SIMD (single instruction, multiple data flow) architecture with very simple and regular array structure. Actually, the architecture is realized by a content-addressable memory (CAM). The authors design almost-linear algorithms for several NP-complete problems by this approach and estimate the performance and limitation. The computation time of the parallel algorithm for the knapsack problem using the CAM is evaluated, and it is shown that the parallel algorithm is 100 or 1000 times faster than the sequential algorithms.

元の言語英語
ホスト出版物のタイトルProceedings - IEEE International Symposium on Circuits and Systems
出版者Publ by IEEE
ページ333-336
ページ数4
ISBN(印刷物)9517212399
出版物ステータス出版済み - 12 1 1988
外部発表Yes

出版物シリーズ

名前Proceedings - IEEE International Symposium on Circuits and Systems
1
ISSN(印刷物)0271-4310

    フィンガープリント

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering

これを引用

Yasuura, H., Tsujimoto, T., & Tamaru, K. (1988). Parallel exhaustive search for several np-complete problems using content addressable memories. : Proceedings - IEEE International Symposium on Circuits and Systems (pp. 333-336). (Proceedings - IEEE International Symposium on Circuits and Systems; 巻数 1). Publ by IEEE.