To satisfy the ever-increasing requirement from load side and improve the power quality through harmonic content reduction, the paralleled converters' structure is seen to be an interesting solution. However, paralleled converters, in which the same dc and ac sides are shared, suffer from a major challenge related to the excessive circulating currents due to the difference in the induced common-mode voltage (CMV) in each converter. This voltage difference is due to the instantaneous potential difference between paralleled phase-legs, due to the discrepancy in circuit and control parameters of paralleled converters. Consequently, zero-sequence circulating current (ZSCC) as well as differential-mode circulating current (DMCC) shall appear between the paralleled converters. In this context, this article utilizes the interleaved pulsewidth modulation (PWM) concept for the ZSCC and DMCC reduction in paralleled split-source inverters (SSIs), where this SSI is a single-stage dc-ac converter and the prior mentioned operation and associated issues have not been investigated yet. This article describes the three-phase SSI structure and its basic operation, and shows the corresponding CMV waveform. Then, based on the shown analysis, an interleaved discontinuous PWM strategy is proposed to restrain the CMV amplitude and reduce the induced circulating currents. Furthermore, the effect of changing the modulation index and interleaving angle on the overall converter behavior has also been evaluated in case of using SSI. The analysis and simulations revealed the effectiveness of the proposed modulation strategy compared to counterparts. Finally, the shown simulation results are validated with an experimental prototype of 1 kW.
All Science Journal Classification (ASJC) codes
- Electrical and Electronic Engineering